Question

我有一个非常简单的问题，但我不知道出了什么问题。从本质上讲，在模拟它时，整个过程都可以正常工作硬件给我错误的结果。基本上我有两个ctrl信号确定实体的行为：

 GET   (ctrl = "00000000") sets register tx to input of op1
 SH1_L (ctrl = "00000001") outputs (op1 << 1) or register tx
                           shifts register tx to the right by 31 bits  (tx >> 31)


  library ieee;
  use ieee.std_logic_1164.all;

  entity test is
  port
  (
    op1    : in  std_logic_vector(31 downto 0);      -- First input operand
    ctrl   : in std_logic_vector(7 downto 0);        -- Control signal
    clk    : in  std_logic;                          -- clock
    res    : out std_logic_vector(31 downto 0)       -- Result
  );
  end;

  architecture rtl of test is

    type res_sel_type is (GET, SH1_L); 

    constant Z : std_logic_vector(31 downto 0) := (others => '0');                        

    signal res_sel  : res_sel_type;
    signal load     : std_logic := '0';
    signal shl      : std_logic := '0';

    signal tx       : std_logic_vector(31 downto 0) := (others => '0');
    signal inp1     : std_logic_vector(31 downto 0) := (others => '0');

  begin

    dec_op: process (ctrl, op1)
    begin  

        res_sel  <= GET;
      load     <= '0';
      shl      <= '0';
      inp1     <= ( others => '0');

      case ctrl is

         -- store operand 
             when "00000000" =>
                inp1    <= op1;             
                load    <= '1';          
                res_sel <= GET;

             -- 1-bit left-shift with carry 
             when "00000001" =>
              inp1    <= op1;
          shl     <= '1'; 
                res_sel <= SH1_L;

             when others =>
                -- Leave default values

             end case;                  

    end process;

    -- Selection of output
    sel_out: process (res_sel, inp1) 
    begin

      case res_sel is

       when GET => NULL;  

       when SH1_L =>
        res  <= ( inp1(30 downto 0) & '0' ) or tx;

         when others =>
            res <= (others => '0');

      end case;

    end process;

    sync: process(clk)
    begin       
     if clk'event and clk = '1' then
          if load = '1' then  
             tx <= op1;
          elsif shl = '1' then
             tx <= Z(30 downto 0) & op1(31);
          end if;      
     end if;
    end process;  

  end rtl;

TESTPROGRAM

GET  0
SH1_L 0xfedcba90    exp. output: 0xfdb97520  act. output = 0xfdb97521
SH1_L 0x7654321f    exp. output: 0xeca8643f  act. output = 0xeca8643e
SH1_L 0x71234567    exp. output: 0xe2468ace  act. output = 0xe2468ace

正如你所看到的，最后一点是出于某种原因是错误的。我必须有所收获时序错误，因此寄存器tx首先在其实际写入之前写入用于计算输出。

任何人都知道如何解决这个问题？

非常感谢！

Answer 1

您是否忘记了过程敏感度列表中的tx信号？

screenshot of Sigasi HDT

Answer 2

res未在组合过程中的所有条件下定义。因此，您可能会在合成结果中使用逻辑门控锁存器。永远不是一个好主意。

首先通过提供默认分配来删除它们。

模拟与硬件不匹配

2 个答案: