Question

我收到此错误：

# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.acc(behavioralreg)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.alu(arc)
# Loading work.ar(behavioralreg)
# Loading work.controlunit(arc)
# Loading work.ir(behavioralreg)
# Loading work.memory(behv)
# Loading work.pc(behavioralreg)
# Loading work.processor(arc)

-----------现在出现错误-------------

# ** Failure: (vsim-3807) Types do not match between component and entity for port "address".
#    Time: 0 ns  Iteration: 0  Instance: /processor/memmap File: C:/Users/dell/Desktop/PROESSORS/VHDL Codes_1/333CO10_Proc.vhdl/memory.vhd Line: 10
# ** Error: (vsim-3733) C:/Users/dell/Desktop/PROESSORS/VHDL Codes_1/333CO10_Proc.vhdl/processor.vhd(187): No default binding for component at 'memmap'.
#  (Generic 'words' is not on the entity.)
#         Region: /processor/memmap
# ** Error: (vsim-3733) C:/Users/dell/Desktop/PROESSORS/VHDL Codes_1/333CO10_Proc.vhdl/processor.vhd(187): No default binding for component at 'memmap'.
#  (Generic 'bits' is not on the entity.)
#         Region: /processor/memmap
# Fatal error in Process rea at C:/Users/dell/Desktop/PROESSORS/VHDL Codes_1/333CO10_Proc.vhdl/memory.vhd line 50
#  while elaborating region: /processor/memmap
# Fatal error in Process line__201 at C:/Users/dell/Desktop/PROESSORS/VHDL Codes_1/333CO10_Proc.vhdl/processor.vhd line 201
#  while elaborating region: /processor

什么是错误？我已经多次检查但没有得到错误的观点。我是VHDL的初学者。

我的代码：

library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_unsigned.all;

entity processor is
end processor;

architecture arc of processor is
---some code
component memory

generic( bits : INTEGER:=8;
         words :INTEGER:=256);  

port (  
    enable      :   in std_logic;
        read        :   in std_logic;
        write       :   in std_logic;
        address :   in INTEGER range 0 to words-1;
        data_in :   in std_logic_vector(15 downto 0);
        data_out:   out std_logic_vector(15 downto 0)
);
end component;
--some code
signal MEMenable        : std_logic:='0';
signal  MEMread     :   std_logic:='0';
signal  MEMwrite        :   std_logic:='0';
signal MEMaddr  :    INTEGER range 0 to 255;
signal  MEMdata_in  :   std_logic_vector(15 downto 0):="0000000000000000";
signal  MEMdata_out:     std_logic_vector(15 downto 0):="0000000000000000";
signal clk: bit ;
  signal clocktime :integer range 0 to 10 :=0;
  signal rst : bit :='0';
--now PORT MAPPING COMPONENTS-----
begin
--- some code
MEMmap: memory port map(    
        enable=>MEMenable   ,
        read=>MEMread   ,
        write=>MEMwrite,
        address=>MEMaddr    ,
        data_in=>MEMdata_in ,
        data_out=>MEMdata_out
);
--- some code

和记忆是：

library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_unsigned.all;
entity memory is
port (
    enable      :   in std_logic;
        read        :   in std_logic;
        write   :   in std_logic;
        address :   in std_logic_vector(7 downto 0);
        data_in :   in std_logic_vector(15 downto 0);
        data_out:   out std_logic_vector(15 downto 0)
);
end memory;

architecture behv of memory is          

  type ram_type is array (0 to 255) of 
                std_logic_vector(15 downto 0);
  signal tmp_ram: ram_type;

begin

    writ: process(enable, read, address, data_in)
    begin
    ---some code
    end process;
end behv;

所有文件：如果您想要完整的代码，请问我。

Answer 1

您在架构中引用的组件“内存”需要具有完全相同的端口类型，而代码中并非如此。

在组件中，地址类型为“整数范围...”，而内存实体使用普通的std_logic_vector ...

模拟MODELSIM期间VHDL类型不匹配

1 个答案: