我在使用ModelSim中的VHDL模拟代码时遇到了问题，代码的目的是对两个数字进行求和和减法，表示为向量并将结果存储在另外两个向量中。但是，当我开始模拟时，输出向量保持未分配的值“U”。这段代码是由我的教授编写的，所以我相信它没有错误，但我不知道如何让输出得到我想要的结果。代码及其测试平台在这里：
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity addsub is
port (
\a\ : out std_logic_vector(31 downto 0);
\s\ : out std_logic_vector(31 downto 0);
\x\ : in std_logic_vector(31 downto 0);
\y\ : in std_logic_vector(31 downto 0)
);
end addsub;
architecture behavior of addsub is
component add_op_s
generic (
w_in1 : integer := 8;
w_in2 : integer := 8;
w_out : integer := 16
);
port (
I0 : in std_logic_vector(w_in1-1 downto 0);
I1 : in std_logic_vector(w_in2-1 downto 0);
O0 : out std_logic_vector(w_out-1 downto 0)
);
end component;
component sub_op_s
generic (
w_in1 : integer := 16;
w_in2 : integer := 16;
w_out : integer := 32
);
port (
I0 : in std_logic_vector(w_in1-1 downto 0);
I1 : in std_logic_vector(w_in2-1 downto 0);
O0 : out std_logic_vector(w_out-1 downto 0)
);
end component;
signal s5 : std_logic_vector(31 downto 0);
signal s3 : std_logic_vector(31 downto 0);
signal s4 : std_logic_vector(31 downto 0);
signal s2 : std_logic_vector(31 downto 0);
begin
\x_sub_op_s_y\: sub_op_s
generic map (
w_in1 => 32,
w_in2 => 32,
w_out => 32
)
port map (
I0 => s3,
I1 => s4,
O0 => s5
);
\x_add_op_s_y\: add_op_s
generic map (
w_in1 => 32,
w_in2 => 32,
w_out => 32
)
port map (
I0 => s3,
I1 => s4,
O0 => s2
);
s3 <= \x\;
s4 <= \y\;
\a\ <= s2;
\s\ <= s5;
end behavior;
测试平台
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity t_addsub is
end t_addsub;
architecture behavior of t_addsub is
component addsub
port (
\a\ : out std_logic_vector(31 downto 0);
\s\ : out std_logic_vector(31 downto 0);
\x\ : in std_logic_vector(31 downto 0);
\y\ : in std_logic_vector(31 downto 0)
);
end component;
signal \a\ : std_logic_vector(31 downto 0) := (others => '0');
signal \s\ : std_logic_vector(31 downto 0) := (others => '0');
signal \x\ : std_logic_vector(31 downto 0) := (others => '0');
signal \y\ : std_logic_vector(31 downto 0) := (others => '0');
begin
uut: addsub
port map (
\a\ => \a\,
\s\ => \s\,
\x\ => \x\,
\y\ => \y\
);
x_atribution: process
begin
wait for 10 ns;
wait for 10 ns;
\x\ <= conv_std_logic_vector(1,32);
wait for 10 ns;
\x\ <= conv_std_logic_vector(2,32);
wait for 10 ns;
\x\ <= conv_std_logic_vector(3,32);
wait for 10 ns;
\x\ <= conv_std_logic_vector('X', 32);
wait;
end process x_atribution;
y_atribution: process
begin
wait for 10 ns;
wait for 10 ns;
\y\ <= conv_std_logic_vector(3,32);
wait for 10 ns;
\y\ <= conv_std_logic_vector(2,32);
wait for 10 ns;
\y\ <= conv_std_logic_vector(1,32);
wait for 10 ns;
\y\ <= conv_std_logic_vector('X', 32);
wait;
end process y_atribution;
process
begin
wait for 10 ns;
wait on \s\;
assert \a\ = conv_std_logic_vector(4,32)
report "value different from the expected" severity error;
assert false report "end of test of \a\" severity note;
wait;
end process;
process
begin
wait for 10 ns;
wait on \s\;
assert \s\ = conv_std_logic_vector(-2,32)
report "value different from the expected" severity error;
wait on \s\;
assert \s\ = conv_std_logic_vector(0,32)
report "value different from the expected" severity error;
wait on \s\;
assert \s\ = conv_std_logic_vector(2,32)
report "value different from the expected" severity error;
assert false report "end of test of \s\" severity note;
wait;
end process;
process
begin
wait for 10 ns;
wait on \a\;
assert \a\ = conv_std_logic_vector(4,32)
report "value different from the expected" severity error;
wait for 12 ns;
assert \a\ = conv_std_logic_vector(4,32)
report "value different from the expected" severity error;
wait for 10 ns;
assert \a\ = conv_std_logic_vector(4,32)
report "value different from the expected" severity error;
assert false report "end of test of \a\" severity note;
wait;
end process;
process
begin
wait for 10 ns;
wait on \s\;
assert \s\ = conv_std_logic_vector(-2,32)
report "value different from the expected" severity error;
wait for 12 ns;
assert \s\ = conv_std_logic_vector(0,32)
report "value different from the expected" severity error;
wait for 10 ns;
assert \s\ = conv_std_logic_vector(2,32)
report "value different from the expected" severity error;
assert false report "end of test of \s\" severity note;
wait;
end process;
end behavior;
非常感谢你。