我在行为和RTL模型中编写了16位ALU的代码。它没有任何编译或模拟错误，但是当我点击波形窗口中的运行按钮时，它甚至没有显示任何输入或输出，甚至没有时钟。
这是我为它创建的测试平台：
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
Use IEEE.NUMERIC_STD.UNSIGNED;
use ieee.std_logic_textio.all;
USE WORK.ANU.ALL;
entity xalu_tb is
end xalu_tb;
architecture beh of xalu_tb is
component bitalu
Port (A, B, CIN : in STD_LOGIC_VECTOR(15 DOWNTO 0);
CLK, RST : IN STD_LOGIC;
OPCODE : OPCODE1;
RES : OUT STD_LOGIC_VECTOR (31 downto 0);
CARRY, GT, LT, EQ, NEQ : OUT STD_LOGIC
);
end component;
component alurtl
port
(
data1, data2 : in std_logic_vector(15 downto 0);
operation : in bit_vector(3 downto 0);
result : out std_logic_vector(31 downto 0);
carry1, equal, nequal, grt, lrt : out std_logic
);
end component;
signal A, B, CIN : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal clk, rst : STD_LOGIC;
signal opcode : opcode1;
signal res : STD_LOGIC_VECTOR (31 downto 0);
signal CARRY, GT, LT, EQ, NEQ : STD_LOGIC;
signal data1, data2 : std_logic_vector(15 downto 0);
signal operation : bit_vector(3 downto 0);
signal result : std_logic_vector(31 downto 0);
signal carry1, equal, nequal, grt, lrt : std_logic;
file InFile : text open read_mode is "C:/Users/---/Desktop/response.txt";
file OutFile : text open write_mode is "C:/Users/---/Desktop/response1.txt";
begin
u_x : bitalu port map(A, B, CIN, CLK, RST, OPCODE, RES, CARRY, GT, LT, EQ, NEQ);
u_xx : alurtl port map(data1, data2, operation, result, carry1, equal, nequal, grt, lrt);
A <= "0000000000001010";
B <= "0000000000000110";
CIN <= "0000000000000000";
DATA1 <= "0000000000001010";
DATA2 <= "0000000000000110";
CREATE_CLOCK : process
begin
if (rst <= '1') then
res <= "00000000000000000000000000000000";
result <= "00000000000000000000000000000000";
else
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end if;
end process;
p1 : process
variable res : std_logic_vector(31 downto 0);
variable result : std_logic_vector(31 downto 0);
variable lt, gt, eq, neq, lrt, grt, equal, nequal : std_logic;
variable L1, L2 : line;
begin
wait until clk = '1' and clk'event;
OPCODE <= ADD;
operation <= "0000";
if(not (endfile(infile))) then
readLine(infile, L1);
readLine(infile, L2);
read(L1, res);
read(L2, result);
assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
write(L1, RES);
writeline(outfile, L1);
write(L2, result);
writeline(outfile, L2);
end if;
wait for 10 ns;
OPCODE <= sub;
operation <= "0001";
if(not (endfile(infile))) then
readLine(infile, L1);
readLine(infile, L2);
read(L1, res);
read(L2, result);
assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
write(L1, RES);
writeline(outfile, L1);
write(L2, result);
writeline(outfile, L2);
end if;
wait for 10 ns;
OPCODE <= mul;
operation <= "0010";
if(not (endfile(infile))) then
readLine(infile, L1);
readLine(infile, L2);
read(L1, res);
read(L2, result);
assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
write(L1, RES);
writeline(outfile, L1);
write(L2, result);
writeline(outfile, L2);
end if;
wait for 10 ns;
OPCODE <= comp;
operation <= "0011";
if(res(16) = '1') then
if(not (endfile(infile))) then
readLine(infile, L1);
readLine(infile, L2);
read(L1, lt);
read(L2, lrt);
assert(lt = lrt) report "notmatch"severity error;
write(L1, lt);
writeline(outfile, L1);
end if;
elsif(res = "0000000000000000") then
if(not (endfile(infile))) then
readLine(infile, L1);
readLine(infile, L2);
read(L1, eq);
read(L2, equal);
assert(eq = equal) report "notmatch"severity error;
write(L1, eq);
writeline(outfile, L1);
end if;
else
if(not (endfile(infile))) then
readLine(infile, L1);
readLine(infile, L2);
read(L1, gt);
read(L2, grt);
assert(gt = grt) report "notmatch"severity error;
write(L1, gt);
writeline(outfile, L1);
end if;
end if;
wait for 10ns;
OPCODE <= and16;
operation <= "0100";
if(not (endfile(infile))) then
readLine(infile, L1);
readLine(infile, L2);
read(L1, res);
read(L2, result);
assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
write(L1, RES);
writeline(outfile, L1);
write(L2, result);
writeline(outfile, L1);
end if;
wait for 10 ns;
OPCODE <= or16;
operation <= "0101";
if(not (endfile(infile))) then
readLine(infile, L1);
readLine(infile, L2);
read(L1, res);
read(L2, result);
assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
write(L1, RES);
writeline(outfile, L1);
write(L2, result);
writeline(outfile, L2);
end if;
wait for 10 ns;
OPCODE <= not16;
operation <= "0110";
if(not (endfile(infile))) then
readLine(infile, L1);
readLine(infile, L2);
read(L1, res);
read(L2, result);
assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
write(L1, RES);
writeline(outfile, L1);
write(L2, result);
writeline(outfile, L2);
end if;
wait for 10 ns;
OPCODE <= xor16;
operation <= "0111";
if(not (endfile(infile))) then
readLine(infile, L1);
readLine(infile, L2);
read(L1, res);
read(L2, result);
assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
write(L1, RES);
writeline(outfile, L1);
write(L2, result);
writeline(outfile, L2);
end if;
wait for 10 ns;
OPCODE <= srl16;
operation <= "1000";
if(not (endfile(infile))) then
readLine(infile, L1);
readLine(infile, L2);
read(L1, res);
read(L2, result);
assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
write(L1, RES);
writeline(outfile, L1);
write(L2, result);
writeline(outfile, L1);
end if;
wait for 10 ns;
OPCODE <= sll16;
operation <= "1001";
if(not (endfile(infile))) then
readLine(infile, L1);
readLine(infile, L2);
read(L1, res);
read(L2, result);
assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
write(L1, RES);
writeline(outfile, L1);
write(L2, result);
writeline(outfile, L2);
end if;
wait for 10 ns;
OPCODE <= sra16;
operation <= "1010";
if(not (endfile(infile))) then
readLine(infile, L1);
readLine(infile, L2);
read(L1, res);
read(L2, result);
assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
write(L1, RES);
writeline(outfile, L1);
write(L2, result);
writeline(outfile, L2);
end if;
wait for 10 ns;
operation <= "1011";
OPCODE <= sla16;
if(not (endfile(infile))) then
readLine(infile, L1);
readLine(infile, L2);
read(L1, res);
read(L2, result);
assert(res(15 downto 0) = result(15 downto 0)) report "notmatch"severity error;
write(L1, RES);
writeline(outfile, L1);
write(L2, result);
writeline(outfile, L2);
end if;
wait for 10 ns;
end process;
end beh;
答案 0 :(得分：2)
原因是这个测试台代码部分：
CREATE_CLOCK : process
begin
if (rst <= '1') then
res <= "00000000000000000000000000000000";
result <= "00000000000000000000000000000000";
else
... (code with wait statement)
end if;
end process;
该过程将在相同的模拟时间和delta时重复执行
rst <= '1'最初为TRUE，因为永远不会执行wait语句。
因此，模拟将永远不会发展。必须修复代码以确保
在此过程中执行wait语句。
<强>精化：
如果模拟时间和增量没有提前，例如保持在：
Now: 0 ps Delta: 0
或者稍后的时间和delta，那么原因可能是没有a的过程 从不执行等待的敏感性列表，如：
process is
begin
if FALSE then
wait;
...
或无限循环，如：
while TRUE loop
...
ModelSim不会报告任何警告（如“可能的无限循环：过程 不包含WAIT语句。“）或上述代码的错误，以及 模拟器甚至可能很难通过停止和中断GUI交互来停止。
答案 1 :(得分：2)
我读到了这个例子：
CREATE_CLOCK : process
begin
if (rst <= '1') then
现在，令牌<=有两个含义明确无误，因为它们可以根据上下文区分......
第一个是作为信号分配声明。不是“赋值运算符”，因为与某些语言不同，赋值不是运算符。因此，rst <= '1';和if rst <= '1' then之间不会产生混淆。
第二个含义 - 在表达式中 - 是关系运算符“小于或等于”。这就是你在上面实现的。因此电路将保持复位状态并且永远不会超时，直到rst > '1'（即从不）。
一个单独的问题是该过程对Rst（或其他任何东西！）的变化不敏感，因此它永远不会被唤醒......
尝试
CREATE_CLOCK : process (rst)
begin
if rst = '1' then
至少它会让电路退出复位......
其他一些评论：
丢失非标准库使用子句并使用numeric_std代替......
use IEEE.std_logic_arith.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
布尔表达式周围不需要括号。它们只是杂乱无章，可能是从C继承的。以下是等价的：
if(not (endfile(infile))) then
if not endfile(infile) then
重复的测试平台代码可以通过将公共部分粘贴到过程中并多次调用来改进。如果它被声明为进程的本地（在变量声明之后），它可以看到所有进程状态，或者你可以传递任何你想要的参数。
看起来好像opcode和operation可能重复或具有相同的功能。如果是这样的话，最好消除一个（最好是“操作”）或至少将它们连接在一起：例如
constant operations : array(Opcode1) of std_logic_vector(3 downto 0) := (
Add => "0000",
Sub => "0001", ... );
operation <= operations(Opcode);
答案 2 :(得分：1)
是的你是对的错误是我做了一个信号分配，即如果res＆lt; = 1这个语句正在执行无限循环。因为它正在考虑“＆lt; =”小于或等于。 非常感谢你解决了一切