edit:我只是重新安装了菱形菱形和更新,Active-hdl已自动安装,但是模拟仍然给我同样的错误。当我更改库machXO3时;使用machXO3.all;到库machXO2;使用machXO2.all;它会编译..
我正在尝试为OSCH的简单实现编写测试平台,但无法使测试平台正常工作。
几个月前,我设法使其正常工作,但我丢失了正在处理的文件。
这是我拥有的vhdl代码:
<?xml version="1.0" encoding="utf-8"?>
<soap:Envelope xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xmlns:xsd="http://www.w3.org/2001/XMLSchema"
xmlns:soap="http://schemas.xmlsoap.org/soap/envelope/">
<soap:Header>
<Authentication xmlns="http://tempuri.org/">
<Password>string</Password>
<UserName>string</UserName>
</Authentication>
</soap:Header>
<soap:Body>
<HelloWorld xmlns="http://tempuri.org/" />
</soap:Body>
</soap:Envelope>
这是测试平台,大部分是由晶格生成的,我只添加了stdby <='0';
library ieee;
use ieee.std_logic_1164.all;
-- For Main Clock --
library machXO3;
use machXO3.all;
--------------------
entity Clock is
port (stdby : in std_logic;
osc_int: out std_logic
);
end Clock;
architecture Clock_behav of Clock is
COMPONENT OSCH
-- synthesis translate_off
GENERIC (NOM_FREQ: string := "2.56");
-- synthesis translate_on
PORT (STDBY : IN std_logic;
OSC : OUT std_logic
);
END COMPONENT;
begin
Clock: OSCH
-- synthesis translate_off
GENERIC MAP( NOM_FREQ => "2.56" )
-- synthesis translate_on
PORT MAP ( STDBY => stdby,
OSC => osc_int
);
end Clock_behav;
Lattice-diamond告诉我一切都很好,但是当我在Active-hdl中运行所有内容进行模拟时,出现以下错误:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT Clock
PORT(
stdby : IN std_logic;
osc_int : OUT std_logic
);
END COMPONENT;
SIGNAL stdby : std_logic;
SIGNAL osc_int : std_logic;
BEGIN
-- Please check and add your generic clause manually
uut: Clock PORT MAP(
stdby => stdby,
osc_int => osc_int
);
stdby <= '0';
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
--wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
答案 0 :(得分:0)
看C:\ lscc \ diamond \ 3.10_x64 \ active-hdl \ vlib \,似乎没有machXO3库,但是有machxo,machxo2和machxo3l库。更改库machXO3;使用machXO3.all;到库machXO3l;使用machXO3l.all;对测试平台进行一些小的修改,一切似乎都可以正常进行。
新测试台
-- VHDL Test Bench Created from source file Clock.vhd -- Fri Feb 22 13:56:19 2019
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Lattice recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "source->import"
-- menu in the ispLEVER Project Navigator to import the testbench.
-- Then edit the user defined section below, adding code to generate the
-- stimulus for your design.
-- 3) VHDL simulations will produce errors if there are Lattice FPGA library
-- elements in your design that require the instantiation of GSR, PUR, and
-- TSALL and they are not present in the testbench. For more information see
-- the How To section of online help.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT Clock
PORT(
stdby : IN std_logic;
osc_int : OUT std_logic
);
END COMPONENT;
SIGNAL stdby : std_logic;
SIGNAL osc_int : std_logic;
constant PERIOD : time := 20 ns;
BEGIN
-- Please check and add your generic clause manually
uut: Clock PORT MAP(
stdby => stdby,
osc_int => osc_int
);
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
stdby <= '0';
wait for PERIOD ;
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;