所以我正试图在Vivado为ZYBO FPGA板设计一个'自动售货机'时序电路。但是，每当我尝试通过实现阶段时，我都会遇到一堆错误，主要错误是
[Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than
number of available sites (0).
The following Groups of I/O terminals have not sufficient capacity:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1
has only 0 sites available on device, but needs 1 sites.
Term: clk
我确实尝试过自动I / O规划，但最终做的就是删除引脚约束。它在那时得到了实现，但当然无法生成比特流，因为没有端口被映射到引脚。
这是我的VHDL设计
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY des_src IS
PORT (
reset : IN std_logic;
clk : IN std_logic;
QDN : IN std_logic_vector(2 DOWNTO 0);
PC : OUT std_logic_vector(1 DOWNTO 0)
);
END des_src;
ARCHITECTURE behavioral OF des_src IS
TYPE statetype IS (Start, Five, Ten, Fifteen, Twenty, Twentyfive, Thirty, Thirtyfive, Fourty, Fourtyfive);
SIGNAL currentstate, nextstate : statetype;
BEGIN
fsm1: PROCESS (QDN, currentstate)
BEGIN
CASE currentstate IS
WHEN Start =>
PC <= "00";
CASE QDN IS
WHEN "000" =>
nextstate <= Start;
WHEN "001" =>
nextstate <= Five;
WHEN "010" =>
nextstate <= Ten;
WHEN "100" =>
nextstate <= Twentyfive;
WHEN OTHERS =>
nextstate <= Start;
END CASE;
WHEN Five =>
PC <= "00";
CASE QDN IS
WHEN "000" =>
nextstate <= Five;
WHEN "001" =>
nextstate <= Ten;
WHEN "010" =>
nextstate <= Fifteen;
WHEN "100" =>
nextstate <= Thirty;
WHEN OTHERS =>
nextstate <= Start;
END CASE;
WHEN Ten =>
PC <= "00";
CASE QDN IS
WHEN "000" =>
nextstate <= Ten;
WHEN "001" =>
nextstate <= Fifteen;
WHEN "010" =>
nextstate <= Twenty;
WHEN "100" =>
nextstate <= Thirtyfive;
WHEN OTHERS =>
nextstate <= Start;
END CASE;
WHEN Fifteen =>
PC <= "00";
CASE QDN IS
WHEN "000" =>
nextstate <=Fifteen;
WHEN "001" =>
nextstate <= Twenty;
WHEN "010" =>
nextstate <= Twentyfive;
WHEN "100" =>
nextstate <= Fourty;
WHEN OTHERS =>
nextstate <= Start;
END CASE;
WHEN Twenty =>
PC <= "00";
CASE QDN IS
WHEN "000" =>
nextstate <= Twenty;
WHEN "001" =>
nextstate <= Twentyfive;
WHEN "010" =>
nextstate <= Thirty;
WHEN "100" =>
nextstate <= Fourtyfive;
WHEN OTHERS =>
nextstate <= Start;
END CASE;
WHEN Twentyfive =>
PC <= "10";
nextstate <= Start;
WHEN Thirty =>
PC <= "01";
nextstate <= Twentyfive;
WHEN Thirtyfive =>
PC <= "01";
nextstate <= Thirty;
WHEN Fourty =>
PC <= "01";
nextstate <= Thirtyfive;
WHEN Fourtyfive =>
PC <= "01";
nextstate <= Fourty;
END CASE;
END PROCESS;
fsm2: PROCESS (reset, clk)
BEGIN
IF (reset = '0') THEN
currentstate <= Start;
ELSIF (clk'EVENT) AND (clk = '1') THEN
currentstate <= nextstate;
END IF;
END PROCESS;
END behavioral;
这是我的约束
##Buttons
##IO_L20N_T3_34
set_property IOSTANDARD LVCMOS33 [get_ports {QDN[0]}]
set_property PACKAGE_PIN R18 [get_ports {QDN[0]}]
##IO_L24N_T3_34
set_property IOSTANDARD LVCMOS33 [get_ports {QDN[1]}]
set_property PACKAGE_PIN P16 [get_ports {QDN[1]}]
##IO_L18P_T2_34
set_property IOSTANDARD LVCMOS33 [get_ports {QDN[2]}]
set_property PACKAGE_PIN V16 [get_ports {QDN[2]}]
##IO_L7P_T1_34
set_property IOSTANDARD LVCMOS33 [get_ports reset]
set_property PACKAGE_PIN Y16 [get_ports reset]
##LEDs
##IO_L23P_T3_35
set_property IOSTANDARD LVCMOS33 [get_ports {PC[0]}]
set_property PACKAGE_PIN M14 [get_ports {PC[0]}]
##IO_L23N_T3_35
set_property IOSTANDARD LVCMOS33 [get_ports {PC[1]}]
set_property PACKAGE_PIN M15 [get_ports {PC[1]}]
create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports {QDN[*]}]
set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports {QDN[*]}]
set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset]
set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset]
set_output_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports {PC[*]}]
set_output_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports {PC[*]}]
我正在使用Vivado 2015.2并为ZYBO开发板设计。
感谢任何和所有帮助。
编辑8/26/15
好吧，我的代码大部分都在工作。我能够使用
set_property PACKAGE_PIN L16 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
我的时钟。但是，这个时钟比我想要的速度快（125MHz），所以我知道我必须使用时钟分频并在约束文件中生成一个时钟，但是我需要将生成的时钟分配给一个引脚吗？有没有人有关于如何在我当前的vhdl代码中包含时钟分频器的任何提示？我只是让它成为另一个进程，并添加另一个端口，还是比它更复杂？
答案 0 :(得分：1)
您没有为clk主要分配引脚。我想Vivado认为它需要一个1.8V LVCMOS输入（可能是默认值），但Zybo上没有LVCMOS 1V8用户引脚：唯一的1V8组是501，它已经被以太网，USB OTG完全使用， SD卡，UART和按钮。正如你可能告诉Vivado你正在使用Zybo，它无法单独解决这个问题。
因此，如果您有外部时钟源，将其连接到其中一个pmod连接器，请将相应的引脚声明为LVCMOS3V3并将其分配给clk。另外，如果您希望时钟由处理系统驱动，则必须明确地将4个FCLK PS-PL时钟中的一个连接到设计的clk输入。
在我看来，最简单的方法是将您的设计转换为IP（参见Vivado文档），在块设计中实例化，添加处理系统和您需要的主要I / O并执行布线。