RV64G处理器在重置时启动哪个地址？ 我应该查看哪个scala文件来理解/修改重置向量地址？
我尝试在Top类中为TopIO添加一个简单的printf语句 监视MemIO并生成模拟器。准备好后，valid = true，地址（io.mem.req_cmd.bits.addr） 打印为0x8，标签为（io.mem.req_cmd.bits.tag）= 0x13。 我可以在程序rv64ui-p-add.dump
中的地址0x200处找到获取的指令（在128位宽的io.mem.resp.bits.data中）。所以我假设0x200是处理器的起始地址。这是对的吗？
（a）如果这是正确的，我想知道，address = 0x8和tag = 0x13如何转换为0x200？
（b）生成的地址+标签是32位，我希望它是64位（RV64G架构）。在Configs.scala中，MIFAddrBits设置为26位（取决于PAddrBits（32）和CacheBlocOffsetBits（log2Up（64））。为什么这些设置如此？
（c）中 仿真模式下以详细模式显示的PC地址为40位，但寄存器为64位。 为什么单独的PC地址只显示40位？模拟器输出的一部分如下所示。
C0: 66 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 67 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 68 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 69 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 70 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Addr (io.mem.req_cmd.bits.addr) - 0x0000008 :: Tag (io.mem.req_cmd.bits.tag) - 0x13 :: rw (io.mem.req_cmd.bits.rw)- 0
C0: 71 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 72 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 73 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 74 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 75 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 76 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 77 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 78 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
...
...
...
C0: 99 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 100 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Mem Response data(io.mem.resp.bits.data) - 0x00054863f000257300051063f1002573 :: Tag (io.mem.resp.bits.tag) - 0x13
C0: 101 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Mem Response data(io.mem.resp.bits.data) - 0x000002975440006f00100e130ff0000f :: Tag (io.mem.resp.bits.tag) - 0x13
C0: 102 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Mem Response data(io.mem.resp.bits.data) - 0x1f8002931012907300028463de428293 :: Tag (io.mem.resp.bits.tag) - 0x13
C0: 103 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Mem Response data(io.mem.resp.bits.data) - 0x3412907301428293000002973002b073 :: Tag (io.mem.resp.bits.tag) - 0x13
C0: 104 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 105 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 106 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 107 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 108 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 109 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 110 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 111 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 112 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 113 [1] pc=[0000000200] W[r10=0000000000000000][1] R[r 0=0000000000000000] R[r16=f4a91906b99f921b] inst=[f1002573] csrr a0, mhartid
C0: 114 [0] pc=[0000000200] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r16=f4a91906b99f921b] inst=[f1002573] csrr a0, mhartid
C0: 115 [0] pc=[0000000200] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r16=f4a91906b99f921b] inst=[f1002573] csrr a0, mhartid
C0: 116 [1] pc=[0000000204] W[r 0=0000000000000000][0] R[r10=0000000000000000] R[r 0=0000000000000000] inst=[00051063] bnez a0, pc + 0
C0: 117 [1] pc=[0000000208] W[r10=8000000000041129][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[f0002573] csrr a0, mcpuid
C0: 118 [0] pc=[0000000208] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[f0002573] csrr a0, mcpuid
C0: 119 [0] pc=[0000000208] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[f0002573] csrr a0, mcpuid
C0: 120 [1] pc=[000000020c] W[r 0=0000000000000001][0] R[r10=8000000000041129] R[r 0=0000000000000000] inst=[00054863] bltz a0, pc + 16
C0: 121 [0] pc=[000000020c] W[r 0=0000000000000001][0] R[r10=0000000000000000] R[r 0=f4a91906b99f921b] inst=[00054863] bltz a0, pc + 16
...
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...
答案 0 :(得分：3)
相关的架构仍在草案中，这种定义现在已经改变。 请参阅latest privileged ISA spec
正如我写的那样，V1.10是最新的草案。从第3.3节重置＆＃39;
将pc设置为实现定义的重置向量。
所以实现可以做他们想做的事。
[顺便提一下，这个草案继续在3.3节的评论段落中假设复位向量与陷阱基向量不同（在mtvec中）。但是，正文中不禁止将它们设置为相同的值。]
答案 1 :(得分：1)
引用RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.7（第3.1.9节）：
对于陷阱向量的高位和低位，标准复位向量分别为0xF ... FFF00或0x0 ... 0200。
在Rocket中，这是通过将START_ADDR设置为0x200来实现的 src/main/scala/package.scala：
val MTVEC = 0x100
val START_ADDR = MTVEC + 0x100