对于火箭芯片，我想构建一个能够生成波形的C仿真器。所以我按照说明操作：
$ cd emulator
$ make debug
但是我收到以下错误（gcc版本是5.3.1 20160413，操作系统是Ubuntu-16.04）：
jiaxun@ubuntu:~/rocket-chip/emulator$ make debug
cd /home/jiaxun/rocket-chip && java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar sbt-launch.jar "project rocketchip" "run rocketchip
Top DefaultCPPCofig --W0W --minimumCompatibility 3.0.0 --backend c --configName DefaultCPPConfig --
compileInitializationUnoptimized --targetDir /home/jiaxun/rocet-chip/emulator/generated-src --noIoDebug"
Java HotSpot(TM) 64-Bit Server VM warning: ignoring option MaxPermSize=256M; support was removed in 8.0
[info] Loading project definition from /home/jiaxun/rocket-chip/project
Using addons:
[info] Set current project to rocketchip (in build file:/home/jiaxun/rocket-chip/)
[info] Set current project to rocketchip (in build file:/home/jiaxun/rocket-chip/)
[info] Running rocketchip.TestGenerator rocketchip Top DefaultCPPConfig --W0W --minimumCompatibility 3.0.0 --backend c --
configName DefaultCPPCofig --compileInitializationUnoptimized --targetDir /home/jiaxun/rocket-chip/emulator/generated-src --
noIoDebug
Generated Address Map
mem 0 - 3fffffff
conf:devicetree 40000000 - 40007fff
conf:csr0 40008000 - 4000ffff
conf:csr1 40010000 - 40017fff
conf:scr 40018000 - 400181ff
Generated Configuration String
platform {
vendor ucb;
arch rocket;
};
ram {
0 {
addr 0;
size 0x40000000;
};
};
core {
0 {
0 {
isa rv64;
addr 0x40008000;
};
};
1 {
0 {
isa rv64;
addr 0x40010000;
};
};
};
UNCORE_SCR: 40018000 -> N_CORES
UNCORE_SCR: 40018001 -> MMIO_BASE
UNCORE_SCR: 40018002 -> MEMORY_CHANNEL_MUX_SELECT
UNCORE_SCR: 4001803f -> HTIF_IO_CLOCK_DIVISOR
CPP elaborate
[info] [8.337] // COMPILING < (class rocketchip.Top)>(12)
[info] [9.003] giving names
[info] [9.453] executing custom transforms
[info] [9.454] convert masked writes of inline mems
[info] [9.721] adding clocks and resets
[info] [11.000] inferring widths
[info] [11.577] eliminating W0W (pre width check)
[info] [11.845] checking widths
[info] [12.019] eliminating W0W (post width check)
[info] [12.313] lowering complex nodes to primitives
[info] [12.313] removing type nodes
[info] [12.540] compiling 105641 nodes
[info] [12.540] computing memory ports
[info] [12.860] resolving nodes to the components
[info] [14.166] creating clock domains
[info] [14.281] pruning unconnected IOs
[info] [14.305] checking for combinational loops
[info] [14.598] NO COMBINATIONAL LOOP FOUND
[info] [14.967] populating clock domains
CppBackend::elaborate: need 1317, redundant 1028 shadow registers
[info] [15.820] generating cpp files
CppBackend: createCppFile Top.DefaultCPPConfig-0.cpp
CppBackend: createCppFile Top.DefaultCPPConfig-1.cpp
CppBackend: createCppFile Top.DefaultCPPConfig-2.cpp
[warn] converters.scala:127: UNABLE TO FIND manager_id IN <ClientTileLinkNetworkPort (class uncore.ClientTileLinkNetworkPort)>
in class uncore.CientTileLinkNetworkPort
[warn] converters.scala:127: UNABLE TO FIND manager_id IN <ClientTileLinkNetworkPort_1 (class
uncore.ClientTileLinkNetworkPort)> in class uncoreClientTileLinkNetworkPort
[warn] converters.scala:208: UNABLE TO FIND client_id IN <ManagerTileLinkNetworkPort (class uncore.ManagerTileLinkNetworkPort)>
in class uncore.anagerTileLinkNetworkPort
[warn] converters.scala:210: UNABLE TO FIND client_id IN <ManagerTileLinkNetworkPort (class uncore.ManagerTileLinkNetworkPort)>
in class uncore.anagerTileLinkNetworkPort
[warn] converters.scala:208: UNABLE TO FIND client_id IN <ManagerTileLinkNetworkPort_1 (class
uncore.ManagerTileLinkNetworkPort)> in class uncor.ManagerTileLinkNetworkPort
[warn] converters.scala:210: UNABLE TO FIND client_id IN <ManagerTileLinkNetworkPort_1 (class
uncore.ManagerTileLinkNetworkPort)> in class uncor.ManagerTileLinkNetworkPort
[warn] NastiROM.scala:28: UNABLE TO FIND data IN <Queue (class Chisel.Queue)> in class uncore.NastiROM
[warn] NastiROM.scala:28: UNABLE TO FIND last IN <Queue (class Chisel.Queue)> in class uncore.NastiROM
[warn] NastiROM.scala:28: UNABLE TO FIND resp IN <Queue (class Chisel.Queue)> in class uncore.NastiROM
[warn] nbdcache.scala:538: UNABLE TO FIND data IN <replay_arb (class Chisel.Arbiter)> in class rocket.MSHRFile
[warn] nbdcache.scala:538: UNABLE TO FIND data IN <replay_arb (class Chisel.Arbiter)> in class rocket.MSHRFile
[warn] Testing.scala:206: Width.op- setting width to Width(0): 1 < 10 in class rocketchip.TestGenerator$
[warn] Testing.scala:206: Width.op- setting width to Width(0): 1 < 10 in class rocketchip.TestGenerator$
[success] Total time: 19 s, completed Apr 28, 2016 9:09:39 AM
cd /home/jiaxun/rocket-chip && java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar sbt-launch.jar "project rocketchip" "run rocketchip
Top DefaultCPPCofig --W0W --minimumCompatibility 3.0.0 --backend c --configName DefaultCPPConfig --
compileInitializationUnoptimized --targetDir /home/jiaxun/rocet-chip/emulator/generated-src-debug --debug --vcd --ioDebug"
Java HotSpot(TM) 64-Bit Server VM warning: ignoring option MaxPermSize=256M; support was removed in 8.0
[info] Loading project definition from /home/jiaxun/rocket-chip/project
Using addons:
[info] Set current project to rocketchip (in build file:/home/jiaxun/rocket-chip/)
[info] Set current project to rocketchip (in build file:/home/jiaxun/rocket-chip/)
[info] Running rocketchip.TestGenerator rocketchip Top DefaultCPPConfig --W0W --minimumCompatibility 3.0.0 --backend c --
configName DefaultCPPCofig --compileInitializationUnoptimized --targetDir /home/jiaxun/rocket-chip/emulator/generated-src-debug
--debug --vcd --ioDebug
Generated Address Map
mem 0 - 3fffffff
conf:devicetree 40000000 - 40007fff
conf:csr0 40008000 - 4000ffff
conf:csr1 40010000 - 40017fff
conf:scr 40018000 - 400181ff
Generated Configuration String
platform {
vendor ucb;
arch rocket;
};
ram {
0 {
addr 0;
size 0x40000000;
};
};
core {
0 {
0 {
isa rv64;
addr 0x40008000;
};
};
1 {
0 {
isa rv64;
addr 0x40010000;
};
};
};
UNCORE_SCR: 40018000 -> N_CORES
UNCORE_SCR: 40018001 -> MMIO_BASE
UNCORE_SCR: 40018002 -> MEMORY_CHANNEL_MUX_SELECT
UNCORE_SCR: 4001803f -> HTIF_IO_CLOCK_DIVISOR
CPP elaborate
[info] [8.811] // COMPILING < (class rocketchip.Top)>(12)
[info] [9.412] giving names
[info] [9.913] executing custom transforms
[info] [9.914] convert masked writes of inline mems
[info] [10.177] adding clocks and resets
[info] [10.495] inferring widths
[info] [11.135] eliminating W0W (pre width check)
[info] [11.385] checking widths
[info] [11.562] eliminating W0W (post width check)
[info] [11.747] lowering complex nodes to primitives
[info] [11.747] removing type nodes
[info] [12.022] compiling 105641 nodes
[info] [12.022] computing memory ports
[info] [12.333] resolving nodes to the components
[info] [13.600] creating clock domains
[info] [13.705] pruning unconnected IOs
[info] [13.728] checking for combinational loops
[info] [14.015] NO COMBINATIONAL LOOP FOUND
[info] [14.333] populating clock domains
CppBackend::elaborate: need 1317, redundant 1028 shadow registers
[info] [15.256] generating cpp files
CppBackend: createCppFile Top.DefaultCPPConfig-0.cpp
CppBackend: createCppFile Top.DefaultCPPConfig-1.cpp
CppBackend: createCppFile Top.DefaultCPPConfig-2.cpp
CppBackend: createCppFile Top.DefaultCPPConfig-3.cpp
[warn] converters.scala:127: UNABLE TO FIND manager_id IN <ClientTileLinkNetworkPort (class uncore.ClientTileLinkNetworkPort)>
in class uncore.CientTileLinkNetworkPort
[warn] converters.scala:127: UNABLE TO FIND manager_id IN <ClientTileLinkNetworkPort_1 (class
uncore.ClientTileLinkNetworkPort)> in class uncoreClientTileLinkNetworkPort
[warn] converters.scala:208: UNABLE TO FIND client_id IN <ManagerTileLinkNetworkPort (class uncore.ManagerTileLinkNetworkPort)>
in class uncore.anagerTileLinkNetworkPort
[warn] converters.scala:210: UNABLE TO FIND client_id IN <ManagerTileLinkNetworkPort (class uncore.ManagerTileLinkNetworkPort)>
in class uncore.anagerTileLinkNetworkPort
[warn] converters.scala:208: UNABLE TO FIND client_id IN <ManagerTileLinkNetworkPort_1 (class
uncore.ManagerTileLinkNetworkPort)> in class uncor.ManagerTileLinkNetworkPort
[warn] converters.scala:210: UNABLE TO FIND client_id IN <ManagerTileLinkNetworkPort_1 (class
uncore.ManagerTileLinkNetworkPort)> in class uncor.ManagerTileLinkNetworkPort
[warn] NastiROM.scala:28: UNABLE TO FIND data IN <Queue (class Chisel.Queue)> in class uncore.NastiROM
[warn] NastiROM.scala:28: UNABLE TO FIND last IN <Queue (class Chisel.Queue)> in class uncore.NastiROM
[warn] NastiROM.scala:28: UNABLE TO FIND resp IN <Queue (class Chisel.Queue)> in class uncore.NastiROM
[warn] nbdcache.scala:538: UNABLE TO FIND data IN <replay_arb (class Chisel.Arbiter)> in class rocket.MSHRFile
[warn] nbdcache.scala:538: UNABLE TO FIND data IN <replay_arb (class Chisel.Arbiter)> in class rocket.MSHRFile
[warn] Testing.scala:206: Width.op- setting width to Width(0): 1 < 10 in class rocketchip.TestGenerator$
[warn] Testing.scala:206: Width.op- setting width to Width(0): 1 < 10 in class rocketchip.TestGenerator$
[success] Total time: 20 s, completed Apr 28, 2016 9:10:05 AM
echo "#ifndef __CONST_H__" > /home/jiaxun/rocket-chip/emulator/generated-src-debug/consts.DefaultCPPConfig.h
echo "#define __CONST_H__" >> /home/jiaxun/rocket-chip/emulator/generated-src-debug/consts.DefaultCPPConfig.h
sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/#define \1 \2/' /home/jiaxun/rocket-chip/emulator/generated-src-
debug/Top.DefaultCPPConfig.prm >> home/jiaxun/rocket-chip/emulator/generated-src-debug/consts.DefaultCPPConfig.h
echo "#define TBFRAG \"Top.DefaultCPPConfig.tb.cpp\"" >> /home/jiaxun/rocket-chip/emulator/generated-src-
debug/consts.DefaultCPPConfig.h
echo "#endif // __CONST_H__" >> /home/jiaxun/rocket-chip/emulator/generated-src-debug/consts.DefaultCPPConfig.h
g++ -O1 -std=c++11 -I/home/jiaxun/riscv_install/include -I/home/jiaxun/rocket-chip/csrc -I/home/jiaxun/rocket-chip/dramsim2 -
include /home/jiaxu/rocket-chip/emulator/generated-src-debug/Top.DefaultCPPConfig.scr_map.h -include /home/jiaxun/rocket-
chip/emulator/generated-src-debug/Top.DefaltCPPConfig.h -include /home/jiaxun/rocket-chip/emulator/generated-src-
debug/consts.DefaultCPPConfig.h -I/home/jiaxun/rocket-chip/emulator/generted-src-debug -c -o emulator.debug.o
/home/jiaxun/rocket-chip/csrc/emulator.cc
g++ -O1 -std=c++11 -I/home/jiaxun/riscv_install/include -I/home/jiaxun/rocket-chip/csrc -I/home/jiaxun/rocket-chip/dramsim2 -
include /home/jiaxu/rocket-chip/emulator/generated-src-debug/Top.DefaultCPPConfig.scr_map.h -include /home/jiaxun/rocket-
chip/emulator/generated-src-debug/Top.DefaltCPPConfig.h -include /home/jiaxun/rocket-chip/emulator/generated-src-
debug/consts.DefaultCPPConfig.h -I/home/jiaxun/rocket-chip/emulator/generted-src-debug -c -o mm.debug.o /home/jiaxun/rocket-
chip/csrc/mm.cc
g++ -O1 -std=c++11 -I/home/jiaxun/riscv_install/include -I/home/jiaxun/rocket-chip/csrc -I/home/jiaxun/rocket-chip/dramsim2 -
include /home/jiaxu/rocket-chip/emulator/generated-src-debug/Top.DefaultCPPConfig.scr_map.h -include /home/jiaxun/rocket-
chip/emulator/generated-src-debug/Top.DefaltCPPConfig.h -include /home/jiaxun/rocket-chip/emulator/generated-src-
debug/consts.DefaultCPPConfig.h -I/home/jiaxun/rocket-chip/emulator/generted-src-debug -c -o mm_dramsim2.debug.o
/home/jiaxun/rocket-chip/csrc/mm_dramsim2.cc
make -j /home/jiaxun/rocket-chip/emulator/generated-src-debug/Top.DefaultCPPConfig-0.o /home/jiaxun/rocket-
chip/emulator/generated-src-debug/TopDefaultCPPConfig-1.o /home/jiaxun/rocket-chip/emulator/generated-src-
debug/Top.DefaultCPPConfig-2.o /home/jiaxun/rocket-chip/emulator/generated-rc-debug/Top.DefaultCPPConfig-3.o
make[1]: Entering directory '/home/jiaxun/rocket-chip/emulator'
g++ -O1 -std=c++11 -I/home/jiaxun/riscv_install/include -I/home/jiaxun/rocket-chip/csrc -I/home/jiaxun/rocket-chip/dramsim2
-c -o /home/jiaxunrocket-chip/emulator/generated-src-debug/Top.DefaultCPPConfig-0.o /home/jiaxun/rocket-
chip/emulator/generated-src-debug/Top.DefaultCPPConfig-0.cp
g++ -O1 -std=c++11 -I/home/jiaxun/riscv_install/include -I/home/jiaxun/rocket-chip/csrc -I/home/jiaxun/rocket-chip/dramsim2
-c -o /home/jiaxunrocket-chip/emulator/generated-src-debug/Top.DefaultCPPConfig-1.o /home/jiaxun/rocket-
chip/emulator/generated-src-debug/Top.DefaultCPPConfig-1.cp
g++ -O1 -std=c++11 -I/home/jiaxun/riscv_install/include -I/home/jiaxun/rocket-chip/csrc -I/home/jiaxun/rocket-chip/dramsim2
-c -o /home/jiaxunrocket-chip/emulator/generated-src-debug/Top.DefaultCPPConfig-2.o /home/jiaxun/rocket-
chip/emulator/generated-src-debug/Top.DefaultCPPConfig-2.cp
g++ -O1 -std=c++11 -I/home/jiaxun/riscv_install/include -I/home/jiaxun/rocket-chip/csrc -I/home/jiaxun/rocket-chip/dramsim2
-c -o /home/jiaxunrocket-chip/emulator/generated-src-debug/Top.DefaultCPPConfig-3.o /home/jiaxun/rocket-
chip/emulator/generated-src-debug/Top.DefaultCPPConfig-3.cp
g++: internal compiler error: Killed (program cc1plus)
Please submit a full bug report,
with preprocessed source if appropriate.
See <file:///usr/share/doc/gcc-5/README.Bugs> for instructions.
<builtin>: recipe for target '/home/jiaxun/rocket-chip/emulator/generated-src-debug/Top.DefaultCPPConfig-0.o' failed
make[1]: *** [/home/jiaxun/rocket-chip/emulator/generated-src-debug/Top.DefaultCPPConfig-0.o] Error 4
make[1]: *** Waiting for unfinished jobs....
g++: internal compiler error: Killed (program cc1plus)
Please submit a full bug report,
with preprocessed source if appropriate.
See <file:///usr/share/doc/gcc-5/README.Bugs> for instructions.
<builtin>: recipe for target '/home/jiaxun/rocket-chip/emulator/generated-src-debug/Top.DefaultCPPConfig-1.o' failed
make[1]: *** [/home/jiaxun/rocket-chip/emulator/generated-src-debug/Top.DefaultCPPConfig-1.o] Error 4
make[1]: Leaving directory '/home/jiaxun/rocket-chip/emulator'
Makefile:29: recipe for target 'Top.DefaultCPPConfig.debug.o' failed
make: *** [Top.DefaultCPPConfig.debug.o] Error
答案 0 :(得分：0)
尝试使用GCC 5选项构建，然后使用make
CC=gcc-5 CXX=g++-5 ./build.sh
答案 1 :(得分：0)
这可能是由于主机上缺少RAM造成的。同样的问题转贴为issue on Github。