DefaultConfig中是否有针对火箭芯片的ECC支持？

Question

我认为，在ECC.scala中，有一种简单的机制可以为ICache和DCache选择ECC编码类型，生成器最终将根据我们分配给“ tagCode”和“ dataCode”。

在Rocket的“ DefaultConfig”中，ICache和DCache的“ tagCode”和“ dataCode”均为“ None”。因此，我认为最终的verilog文件中没有ECC编码。但是我看到最终verilog文件中有许多与ECC相关的代码，例如“ eccmask”。

然后我不知道ECC的支持在Rocket的“ DefaultConfig”中是否有效。

//selector of ECC type
object Code {
    def fromString(s: Option[String]): Code = fromString(s.getOrElse("none"))
    def fromString(s: String): Code = s.toLowerCase match {
        case "none" => new IdentityCode
        case "identity" => new IdentityCode
        case "parity" => new ParityCode
        case "sec" => new SECCode
        case "secded" => new SECDEDCode
        case _ => throw new IllegalArgumentException("Unknown ECC type")
    }
}

//the params of ICache
case class ICacheParams(
    nSets: Int = 64,
    nWays: Int = 4,
    rowBits: Int = 128,
    nTLBEntries: Int = 32,
    cacheIdBits: Int = 0,
    tagECC: Option[String] = None,
    dataECC: Option[String] = None,
    itimAddr: Option[BigInt] = None,
    prefetch: Boolean = false,
    blockBytes: Int = 64,
    latency: Int = 2,
    fetchBytes: Int = 4) extends L1CacheParams {
        def tagCode: Code = Code.fromString(tagECC)
        def dataCode: Code = Code.fromString(dataECC)
        def replacement = new RandomReplacement(nWays)
    }

//the params of ICache
case class DCacheParams(
    nSets: Int = 64,
    nWays: Int = 4,
    rowBits: Int = 64,
    nTLBEntries: Int = 32,
    tagECC: Option[String] = None,
    dataECC: Option[String] = None,
    dataECCBytes: Int = 1,
    nMSHRs: Int = 1,
    nSDQ: Int = 17,
    nRPQ: Int = 16,
    nMMIOs: Int = 1,
    blockBytes: Int = 64,
    acquireBeforeRelease: Boolean = false,
    pipelineWayMux: Boolean = false,
    clockGate: Boolean = false,
    scratch: Option[BigInt] = None) 

extends L1CacheParams {
    def tagCode: Code = Code.fromString(tagECC)
    def dataCode: Code = Code.fromString(dataECC)
    //the final verilog file
    assign data_io_req_bits_eccMask = dataArb_io_out_bits_eccMask;
    assign data_io_req_bits_way_en = dataArb_io_out_bits_way_en;
    assign dataArb_io_in_0_valid = pstore_drain_structural | _T_1732;
    assign dataArb_io_in_0_bits_addr = _T_1829[11:0];
    assign dataArb_io_in_0_bits_wdata = pstore2_valid ? pstore2_storegen_data : a_data;
    assign dataArb_io_in_0_bits_eccMask = {_T_1866,_T_1863};
}