在测试平台中将std_logic转换为整数?

时间:2015-07-29 14:17:07

标签: vhdl xilinx xilinx-ise

我正试图在ISim的控制台窗口中的特定时间返回CLK信号的值(如下面的代码所示,7.5ns)。我收到了这个错误:

  

错误:HDLCompiler:258 - “已保存项目..”第91行:无法转换类型   std_logic输入unsigned

我已经使用 std_logic_vectors 进行了这种转换(integer'image(to_integer(unsigned((generic_signal))));)并且它工作正常,但是这个不会。 CLK值是0或1,我只想在给定时间返回该值。你知道一种更有效的方法吗?你碰巧知道一个链接,我可以看到更多使用'image

返回变量值的方法
   library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use IEEE.NUMERIC_STD.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

-----------------------------------------------------------
-- Component Declaration for the Unit Under Test
-----------------------------------------------------------
component SyncPosEdge port(
   SYS_CLK : in std_logic;
   InputSignal : in std_logic;
   SyncOutputSignal : out std_logic);
end component;

-----------------------------------------------------------
-- Inputs
-----------------------------------------------------------
signal SYS_CLK : std_logic := '0';
signal InputSignal : std_logic := '0';

-----------------------------------------------------------
-- Outputs
-----------------------------------------------------------
signal SyncOutputSignal : std_logic;

-----------------------------------------------------------
-- Clock period definitions
-----------------------------------------------------------
constant SYS_CLK_period : time := 5 ns;
constant InputPeriod : time := 15 ns;

begin

-----------------------------------------------------------
-- Instantiate the Unit Under Test
-----------------------------------------------------------
uut:SyncPosEdge port map(
   SYS_CLK => SYS_CLK,
   InputSignal => InputSignal,
   SyncOutputSignal => SyncOutputSignal);

-----------------------------------------------------------
-- Clock process definitions
-----------------------------------------------------------
SYS_CLK_process:process
begin
   SYS_CLK <= '0';
   wait for SYS_CLK_period / 2;
   SYS_CLK <= '1';
   wait for SYS_CLK_period / 2;
end process SYS_CLK_process;

-----------------------------------------------------------
-- Generate Input Signal
-----------------------------------------------------------
InputGen:process
begin
   InputSignal <= '0';
    wait for InputPeriod / 2;
    InputSignal <= '1';
    wait for InputPeriod / 2;
end process;

-----------------------------------------------------------
-- Stimulus process
-----------------------------------------------------------
stim_proc:process
begin   
   wait for 7.5 ns;
    report "SYS_CLK: " & integer'image(to_integer(unsigned((SYS_CLK))));

   wait;
end process stim_proc;

1 个答案:

答案 0 :(得分:1)

您可以使用std_logic属性轻松打印image

report "SYS_CLK: " & std_logic'image(SYS_CLK);