Question

我试图在这里运行两个7段，我到处搜索但找不到满意的答复，我怎样才能在std_logic中添加1？我也尝试过logic_arith库，但没有任何作用。我在某处读到了我必须使用（0到0）向量，但是我没有真正得到那个部分。这是我的代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_arith.all;

entity blah is
Port ( clk : in  STD_LOGIC;
        anode: out STD_LOGIC_VECTOR (3 downto 0);
        segment: out STD_LOGIC_VECTOR (6 downto 0));
end blah;

architecture Behavioral of blah is
signal sel: STD_LOGIC;
signal r_anode: STD_LOGIC_VECTOR (3 downto 0);
begin
anode <= r_anode;
    process (clk) begin
        if (clk'event and clk = '1') then 
            sel <= sel+1;
        end if;
        end process;

    process (sel) begin
        case sel is 
                when '0' => r_anode <= "1110";
                when '1' => r_anode <= "1101";
                when others => r_anode <= "1111";
                end case;
            case r_anode is
                when "1110" =>  segment <= "0100100";
                when "1101" =>  segment <= "0010010";
                when others => segment <= "1111111";
            end case;
    end process;
    end;

错误

 ERROR:HDLParsers:808 - "E:/Xilinx Projects/blah/blah.vhd" Line 19. + can not have such operands in this context.

Answer 1

sel只是一位，因此添加1就像not sel。

但是，如果sel中的std_logic_vector更多位，则可以添加 natural与std_logic_vector未签名：

sel <= std_logic_vector(unsigned(sel) + 1);

仅使用ieee.numeric_std，因此删除ieee.std_logic_arith std_logic_arith不是标准库（Synopsys专有）。

如何将std_logic添加到整数值

1 个答案: