Question

我有以下问题：

我有一台PC，它为我的SPARTAN 3AN FPGA提供输入，我希望获取这些输入，将它们放在std_logic_vector中，然后将它们转换为整数。指令分为“n”条指令，每条指令32位。我需要将前三位放在一个整数中，接下来的28位放在另一个整数中，最后一位是“最后一条指令标志”。所以，我有两个100个整数的数组，我将在其中放置指令（100是限制）。如果“最后指令标志”为1，则应停止整个操作。

该程序未正确合成，因此我对其进行了模拟。我发现了问题，但我不知道如何解决它，所以我需要你的帮助。这是代码和模拟输出：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.all;


entity BinaryDecimalConv is
end BinaryDecimalConv;

architecture Behavioral of BinaryDecimalConv is

    type int_array is array (100 downto 0) of integer;

    signal clkcnt: integer :=0;
    signal fbaud: integer;
    signal lastnumflag: std_logic:='0';
    signal clk: std_logic;
    signal PLCinput: std_logic;
    signal init: std_logic;
    signal BusyIN: std_logic;
    signal BusyOutSignal: std_logic;
    signal InnerBusyOut: std_logic;
    signal cnt: integer :=0;
    signal fbaut: integer :=0;
    signal pre_int: std_logic_vector (31 downto 0) := (others => '0');
    signal pre_spec_num: int_array := (others =>0);
    signal cylinder: int_array := (others => 0);
    signal InnerNumLength: integer:=0;
    signal num_length: integer:=0;

begin

CLOCKK: Process is
begin
    clk<='0';
    wait for 10 ns;
    clk<='1';
    wait for 10 ns;
end process CLOCKK;

fbaud <=5208;
BusyIN <='0';
init <='0';

PLC: Process is
    variable PrePLC: std_logic_vector(159 downto 0):="1010101010101010101010101001010010101010101010101010101010010100101010101010101010101010100101001010101010101010101010101001010010101010101010101010101010010101"; -- 1 with 100, 5 with 200, 5 2ith 200, 3 with 300, 4 with 750
begin
    PLCinput<=PrePLC(159);
    PrePLC:= PrePLC(158 downto 1) & '0';
    wait for 104166 ns;
end process;    


LastNum: process (LastNumFlag) is
    begin
    if LastNumFlag = '1' then
        BusyOutSignal <='1';
        InnerBusyOut <='1';
    else
        BusyOutSignal <='0';
        InnerBusyOut <='0';
    end if;
    end process LastNum;

DecoderAndAcquirer: process (PLCinput, BusyIN, InnerBusyOut,clk) is
begin

    if (clk'event and clk='1') then                                                         -- If rising edge on clock
        if ((BusyIN='0') and (InnerBusyOut='0') and (init='0')) then                        -- Check if FPGA and PLC are ready to exchange information and if init is done
            if (clkcnt = fbaud/2)                    then                                   --  If clkcnt is equal to half of the duration of the input bit then
                pre_int(31) <= PLCinput;                                                    -- Initialize the last digit of pre_int
                cnt <= cnt+1;                                                               -- Incrementing cnt => going towards bit 2
                clkcnt <=clkcnt+1;                                                          -- Incrementing clkcnt so you can exit this block
                if (cnt<32) then                                                            -- Checking if not last bit
                    pre_int <= '0' & pre_int(31 downto 1);                                  -- If not last bit, shift number to right
                else                                                                        -- else
                    cnt <=0;                                                                -- reset cnt to start with next instruction
                    if (pre_int(0)='1') then                                                -- Check if last digit is one
                        LastNumFlag <= '1';                                                 -- If last digit is one, stop acquiring instructions
                    else
                        LastNumFlag <='0';
                    end if;
                    pre_spec_num(InnerNumLength) <= to_integer(unsigned(pre_int(28 downto 1))); -- Conversion from binary to decimal for instruction
                    cylinder(InnerNumLength) <= to_integer(unsigned(pre_int(31 downto 29)));    -- Conversion from binary to decimal for the number of cylinder
                    InnerNumLength <= InnerNumLength +1;                                            -- Incrementing the number of instructions
                    num_length <= InnerNumLength;
                end if;
            elsif (clkcnt = fbaud) then                                                     -- If clkcnt has reached the entire length of the input bit
                clkcnt <= 0;                                                                -- set clkcnt to zero so the process can start from beginning.
            else                                                                            -- If clkcnt is less than or more than half of the entire duration, but surely
                clkcnt <= clkcnt +1;                                                        -- less than the entire duration, then increment the value of the clkcnt.
            end if;
        end if;
    end if;
end process DecoderAndAcquirer;

end Behavioral;

问题是，如图所示，当cnt发生变化时，指令的第31位没有任何反应。有什么想法吗？

谢谢，博

Simulation

Answer 1

首先PrePLC := PrePLC(158 downto 1) & '0';长度不匹配，所以我假设这应该是PrePLC := PrePLC(158 downto 0) & '0';，因此起作用移位寄存器。

在代码的DecoderAndAcquirer中有：

...
pre_int(31) <= PLCinput;
...
if (cnt<32) then
  pre_int <= '0' & pre_int(31 downto 1);
...

因此，即使通过pre_int(31)分配，它也会在以后被覆盖 pre_int <= '0' & pre_int(31 downto 1); (cnt<32)以来DecoderAndAcquirer: process (PLCinput, BusyIN, InnerBusyOut,clk) is variable pre_int_v : std_logic_vector(pre_int'range); begin if (clk'event and clk='1') then -- If rising edge on clock pre_int_v := pre_int; -- Variable update from signal if ((BusyIN='0') and (InnerBusyOut='0') and (init='0')) then -- Check if FPGA and PLC are ready to exchange information and if init is done if (clkcnt = fbaud/2) then -- If clkcnt is equal to half of the duration of the input bit then pre_int_v(31) := PLCinput; -- Initialize the last digit of pre_int cnt <= cnt+1; -- Incrementing cnt => going towards bit 2 clkcnt <=clkcnt+1; -- Incrementing clkcnt so you can exit this block if (cnt<32) then -- Checking if not last bit pre_int_v := '0' & pre_int_v(31 downto 1); -- If not last bit, shift number to right else -- else cnt <=0; -- reset cnt to start with next instruction if (pre_int_v(0)='1') then -- Check if last digit is one LastNumFlag <= '1'; -- If last digit is one, stop acquiring instructions else LastNumFlag <='0'; end if; pre_spec_num(InnerNumLength) <= to_integer(unsigned(pre_int_v(28 downto 1))); -- Conversion from binary to decimal for instruction cylinder(InnerNumLength) <= to_integer(unsigned(pre_int_v(31 downto 29))); -- Conversion from binary to decimal for the number of cylinder InnerNumLength <= InnerNumLength +1; -- Incrementing the number of instructions num_length <= InnerNumLength; end if; elsif (clkcnt = fbaud) then -- If clkcnt has reached the entire length of the input bit clkcnt <= 0; -- set clkcnt to zero so the process can start from beginning. else -- If clkcnt is less than or more than half of the entire duration, but surely clkcnt <= clkcnt +1; -- less than the entire duration, then increment the value of the clkcnt. end if; end if; pre_int <= pre_int_v; -- Signals update from variable end if; end process DecoderAndAcquirer; pre_int（31）不能再高了。

当模拟较长时间时，cnt变为32，然后在pre_int（31）处显示“1”值;如下图所示。

enter image description here

编辑：下面是带有pre_int临时变量的版本，只是为了显示原理;操作未经验证。

{{1}}

波形图如下所示。

enter image description here

VHDL：Std_Logic输入存储在整数问题中

1 个答案: