具有错误输出的8位全加器（VHDL）

Question

我正在编码VHDL乘法器，需要8位全加器。我使用FAD和HAD（它们工作正常），但8位全加器不返回正确的输出。我的主要问题是输出不正确，因为TestBench上的tS返回Sum + Carry-In的值，它应该只出现在total上。有什么问题？

PS：我试图把一个计数器，然后，代码不起作用，只是一个X出现作为输出。

这是TestBench

library ieee;
use ieee.std_logic_1164.all;

entity FAD7_TB is
end FAD7_TB;

architecture TB of FAD7_TB is
    signal tA: std_logic_vector (7 downto 0);
    signal tB: std_logic_vector (7 downto 0);
    signal tS: std_logic_vector (7 downto 0);
    signal tCi: std_logic;
    signal tCo: std_logic;
    signal total: std_logic_vector (8 downto 0);
begin
    iFAD7: entity work.FAD7 port map(
        A=>tA, B=>tB, S=>tS, Co=>tCo, Ci=>tCi
    );
    process
    begin
        tA<="00000000"; tB <="00000000"; tCi <='0'; wait for 10 ns;
        tA<="00000001"; tB <="00000001"; tCi <='1'; wait for 10 ns;
        tA<="00000011"; tB <="00101010"; tCi <='0'; wait for 10 ns;
        tA<="01100001"; tB <="00010001"; tCi <='1'; wait for 10 ns;
        tA<="01101001"; tB <="11010110"; tCi <='0'; wait for 10 ns;
        tA<="11111111"; tB <="11111111"; tCi <='1'; wait for 50 ns;
    end process;
    total <= tCo & tS;
end TB;

这是“架构”

library ieee;
use ieee.std_logic_1164.all;

entity FAD7 is PORT(
    A: in std_logic_vector (7 downto 0);
    B: in std_logic_vector (7 downto 0);
    Ci: in std_logic;
    S: out std_logic_vector (7 downto 0);
    Co: out std_logic);
end FAD7;

architecture behav_FAD7 of FAD7 is
    signal CoFAD0: std_logic;
    signal CoFAD1: std_logic;
    signal CoFAD2: std_logic;
    signal CoFAD3: std_logic;
    signal CoFAD4: std_logic;
    signal CoFAD5: std_logic;
    signal CoFAD6: std_logic;
    signal CoFAD7: std_logic;
begin
    iFAD0: entity work.FAD port map(
        A=>A(0),
        B=>B(0),
        S=>S(0),
        Ci=> Ci,

    Co =>CoFAD0);

iFAD1: entity work.FAD port map(
    A=>A(1),
    B=>B(1),
    S=>S(1),
    Ci=> CoFAD0,
    Co => CoFAD1);

iFAD2: entity work.FAD port map(
    A=> A(2),
    B=> B(2),
    S=> S(2),
    Ci=> CoFAD1,
    Co => CoFAD2);

iFAD3: entity work.FAD port map(
    A=> A(3),
    B=> B(3),
    S=> S(3),
    Ci=> CoFAD2,
    Co => CoFAD3);

iFAD4: entity work.FAD port map(
    A=> A(4),
    B=> B(4),
    S=> S(4),
    Ci=> CoFAD3,
    Co => CoFAD4);

iFAD5: entity work.FAD port map(
    A=> A(5),
    B=> B(5),
    S=> S(5),
    Ci=> CoFAD4,
    Co => CoFAD5);

iFAD6: entity work.FAD port map(
    A=> A(6),
    B=> B(6),
    S=> S(6),
    Ci=> CoFAD5,
    Co => CoFAD6);
iFAD7: entity work.FAD port map(
    A=> A(7),
    B=> B(7),
    S=> S(7),
    Ci=> CoFAD6,
    Co => Co);
end behav_FAD7;