对于某些数字，16位加法器输出错误的结果

Question

这是我为16位加法器编写的代码 - 这些文件的结果应该与以函数格式编写的加法器进行比较：A + B，所以它们应该有意义。文件已上传here：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Full_Adder_16 is
        Port ( a : in  STD_LOGIC_VECTOR (15 downto 0);
               b : in  STD_LOGIC_VECTOR (15 downto 0);
               s : out  STD_LOGIC_VECTOR (15 downto 0));
    end Full_Adder_16;

    architecture Behavioral of Full_Adder_16 is

    component Full_Adder 
        port(x, y, cin: in std_logic;
        sum, cout: out std_logic);
    end component;

    type cinout is array (0 to 15) of std_logic;
    signal c : cinout;
    signal cout  : STD_LOGIC;

begin

    c(0) <= '0';
    adding: for i in 15 downto 0 generate
        leftmost: if i=15 generate 
            Full_Adder_15: Full_Adder port map (x => a(i), y => b(i), cin => c(i), sum => s(i), cout => cout);
        end generate;
        otherwise: if i/=15 generate 
            Full_Adder_x: Full_Adder port map (x => a(i), y => b(i), cin => c(i), sum => s(i), cout => c(i+1));
        end generate;
    end generate;

    end Behavioral;

这是测试平台：

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity Full_Adder_16_tb is
end;

architecture bench of Full_Adder_16_tb is

  component Full_Adder_16
      Port ( a : in  STD_LOGIC_VECTOR (15 downto 0);
             b : in  STD_LOGIC_VECTOR (15 downto 0);
             s : out  STD_LOGIC_VECTOR (15 downto 0));
  end component;

  signal a: STD_LOGIC_VECTOR (15 downto 0);
  signal b: STD_LOGIC_VECTOR (15 downto 0);
  signal s: STD_LOGIC_VECTOR (15 downto 0);

begin

  uut: Full_Adder_16 port map ( a => a,
                                b => b,
                                s => s );

  stimulus: process
begin

    -- Put initialisation code here
        A <= "0100010010110000";
    B <= "0001010111011110";

    wait for 10 ns;

    A <= "0011000011110111";
    B <= "0100000101000001";

    wait for 10 ns;

    A <= "0000000000000001";
    B <= "0010011000000111";

    wait for 10 ns;

    A <= "0011110010110011";
    B <= "1000111101011110";

    wait for 10 ns;

    A <= "0010000100100001";
    B <= "1111101000100111";

    wait for 10 ns;

    A <= "0001011100100011";
    B <= "0101101101101101";

    wait for 10 ns;

    A <= "1011000110111001";
    B <= "1001011001011111";

    wait for 10 ns;

    A <= "0000001011001010";
    B <= "1000011011101011";

    wait for 10 ns;

    A <= "0011110110100000";
    B <= "1100111000000010";

    wait for 10 ns;

    A <= "0100000111111000";
    B <= "0001001111100101";

    wait for 10 ns;

    A <= "1011111001111100";
    B <= "0100001101010111";

    wait for 10 ns;

    A <= "1111000110000001";
    B <= "1010000100001110";

    wait for 10 ns;

    A <= "0111000111001011";
    B <= "1011000111010100";

    wait for 10 ns;

    A <= "1011011101101010";
    B <= "1100111100101110";

    wait for 10 ns;

    A <= "1111001001010111";
    B <= "0110010000100001";

    wait for 10 ns;

    A <= "0111111101101100";
    B <= "0111000100001111";

    wait for 10 ns;

    A <= "0000111101111000";
    B <= "1100011111101100";

    wait for 10 ns;

    A <= "0011100001100111";
    B <= "1010101100100000";

    wait for 10 ns;

    A <= "1111111101000111";
    B <= "0110111101011100";

    wait for 10 ns;

    A <= "0011111101000001";
    B <= "1100100001100100";

    wait for 10 ns;

    A <= "1011011111000111";
    B <= "1000111101011011";

    wait for 10 ns;

    A <= "1001011010010100";
    B <= "0110001100101111";

    wait for 10 ns;

    A <= "1111111000100101";
    B <= "1111111110001010";

    wait for 10 ns;

    A <= "1011100101000001";
    B <= "0000100000000011";

    -- Put test bench stimulus code here

    wait;
  end process;


end;

我只需要sum值，因为结果将是alu输出。但结果对某些数字来说是错误的，这里是波形：

我使用相同的加法器为乘法器编写代码，但它工作正常。任何解决此问题的意见将不胜感激。

Full_adder如下：

library IEEE;
use IEEE.std_logic_1164.all;

entity Full_Adder is
    port(x, y, cin: in std_logic;
    sum, cout: out std_logic);
end Full_Adder;

architecture my_dataflow of Full_Adder is

begin

sum <= (x xor y) xor cin;
cout  <= (x and y) or (x and cin) or (y and cin);

end my_dataflow;