Question

我很难实例化此代码的fa0部分。我对VHDL很新，所以也许不只是一个答案会有所帮助。

这个Logic 4模块是结构代码，作为我正在研究的ALU的一个组件。

谢谢

-----------------------------------------------------------------
-- 4-bit adder/subtractor module
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity addsub4 is
    port (addl_subh : in std_logic;
        X, Y      : in std_logic_vector(3 downto 0);
        S         : out std_logic_vector(3 downto 0);
        cout, ovf : out std_logic);
end addsub4;

architecture addsub4_arch of addsub4 is

    component fa is
        port (cin, x, y : in std_logic;
            s, cout   : out std_logic);
    end component fa;

    -- let Yhat denote the signal after Y xor addl_subh
    signal Yhat: std_logic_vector(3 downto 0); 
    -- let carryout denote the cout signal for each fa module
    signal carryout: std_logic_vector(3 downto 0); 

begin

    Yhat(0) <= Y(0) xor addl_subh;
    Yhat(1) <= Y(1) xor addl_subh;
    Yhat(2) <= Y(2) xor addl_subh;
    Yhat(3) <= Y(3) xor addl_subh;

    fa0: fa
        port map ( cin => addl_subh, x => X(0), y => Yhat(0),
                s => S(0), cout => carryout(0));

    fa1: fa
        port map ( cin => carryout(0), x => X(1), y => Yhat(1),
                 s => S(1), cout => carryout(1));

    fa2: fa
        port map ( cin => carryout(1), x => X(2), y => Yhat(2),
                 s => S(2), cout => carryout(2));

    fa3: fa
        port map ( cin => carryout(2), x => X(3), y => Yhat(3),
                 s => S(3), cout => carryout(3));

    cout <= carryout(3);
    ovf <= carryout(2) xor carryout(3);

end addsub4_arch;

Answer 1

您的代码没有错误，您应该在项目中添加一个单独的文件，其中包含fa（完整加法器）代码。例如：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY fa IS
PORT(x,y,cin : IN std_logic;
     s,cout  : OUT std_logic);
END ENTITY;

ARCHITECTURE dataflow OF fa IS
begin
    s <= x xor y xor cin;
    cout <= ((x xor y) and cin) or (x and y);
end dataflow;

实例化4位全加器

1 个答案: