Question

所以我想模拟一个简单的寄存器文件并测试它。但它一直很混乱。根据我教授提供的注释，我把我希望的函数寄存器文件放在一起，但现在我正在努力为它创建测试平台。我想主要的是它有两个DATA和ADDR（他展示了一个只有一个内存文件的例子）。

无论如何，对于我的测试平台，我只想在寄存器中写入一些数字，例如在for循环中实例化register1到1，register2到2，依此类推到32，之后我想把它读回来确保一切正确。

这是我到目前为止所拥有的：

Register_File

`include "prj_definition.v"
module REGISTER_FILE_32x32(DATA_R1, DATA_R2, ADDR_R1, ADDR_R2, 
                            DATA_W, ADDR_W, READ, WRITE, CLK, RST);

// input list
input READ, WRITE, CLK, RST;
input [`DATA_INDEX_LIMIT:0] DATA_W;
input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;

// output list
output [`DATA_INDEX_LIMIT:0] DATA_R1;
output [`DATA_INDEX_LIMIT:0] DATA_R2;

reg [`DATA_INDEX_LIMIT:0] data_ret; // return data register 
integer i; // index for reset opeations

reg [`DATA_INDEX_LIMIT:0] DATA_R1;
reg [`DATA_INDEX_LIMIT:0] DATA_R2;
reg [`DATA_INDEX_LIMIT:0] sram_32x32m [0:`MEM_INDEX_LIMIT]; // memory storage

// Parameter for the memory initialization file name
parameter mem_init_file = "mem_content_01.dat";

assign DATA_W = ((READ===1'b1)&&(WRITE===1'b0))?DATA_R1:{`DATA_WIDTH{1'bz} }; //drives the bus during read operation
assign DATA_W = ((READ===1'b1)&&(WRITE===1'b0))?DATA_R2:{`DATA_WIDTH{1'bz} }; //drives the bus during read operation

initial 
begin
DATA_R1 = {`DATA_WIDTH{1'b0} }; //initializing content of all 32 registers as 0
DATA_R2 = {`DATA_WIDTH{1'b0} }; //initializing content of all 32 registers as 0
for(i = 0;i <= `MEM_INDEX_LIMIT; i = i + 1) //up to 32
    sram_32x32m[i] = {`DATA_WIDTH{1'b0}};

end

always @ (negedge RST or posedge CLK)
begin
// TBD: Code for the register file model
if (RST === 1'b0)
begin
for(i = 0;i <= `MEM_INDEX_LIMIT; i = i + 1) //up to 32
    sram_32x32m[i] = {`DATA_WIDTH{1'b0}};

$readmemh(mem_init_file, sram_32x32m);
end
else
begin
 if ((READ===1'b1)&&(WRITE===1'b0))// for read operation
 begin 
    DATA_R1 =  sram_32x32m[ADDR_R1];
    DATA_R2 =  sram_32x32m[ADDR_R2];
 end
 else if ((READ===1'b0)&&(WRITE===1'b1)) // for write operation
    sram_32x32m[ADDR_W] = DATA_W;
end
end
endmodule

register_file_tb

`include "prj_definition.v"
module REGISTER_FILE_TB;

// Storage list
reg [`ADDRESS_INDEX_LIMIT:0] ADDR_R1;
reg [`ADDRESS_INDEX_LIMIT:0] ADDR_R2;
reg [`ADDRESS_INDEX_LIMIT:0] DATA_W;
reg [`ADDRESS_INDEX_LIMIT:0] ADDR_W;

// reset
reg READ, WRITE, RST;

// data register
reg [`DATA_INDEX_LIMIT:0] DATA_REG;
integer i; // index for memory operation
integer no_of_test, no_of_pass;
integer load_data;

// wire lists
wire  CLK;
wire [`DATA_INDEX_LIMIT:0] DATA_R1;
wire [`DATA_INDEX_LIMIT:0] DATA_R2;

assign DATA_R1 = ((READ===1'b0)&&(WRITE===1'b1))?DATA_REG:{`DATA_WIDTH{1'bz} }; //drives the bus during write operation
assign DATA_R2 = ((READ===1'b0)&&(WRITE===1'b1))?DATA_REG:{`DATA_WIDTH{1'bz} }; //drives the bus during write operation

// Clock generator instance
CLK_GENERATOR clk_gen_inst(.CLK(CLK));

// register instantiation
REGISTER_FILE reg_inst(.DATA_R1(DATA_R1), .DATA_R2(DATA_R2), .ADDR_R1(ADDR_R1), .ADDR_R2(ADDR_R2), 
    .DATA_W(), .ADDR_W(), .READ(READ), .WRITE(WRITE), .CLK(CLK), .RST(RST));
endmodule

提前感谢您的帮助！

使用测试平台创建寄存器文件

0 个答案: