Question

I have to creat test bench to my project which contains AXI bus.

I start to write the interface and the transaction for write and read. I read the following blog: http://blog.verificationgentleman.com/2016/08/testing-uvm-drivers-part-2.html?showComment=1471877179631#c7809781639091671746

According this blog the interface should be:

interface vgm_axi_interface(input bit ACLK, input bit ARESETn);
  logic [3:0] AWID;
  logic [31:0] AWADDR;
  logic [3:0] AWLEN;
  logic AWVALID;
  logic AWREADY;


  logic [3:0] WID;
  logic [31:0] WDATA;
  logic WLAST;
  logic WVALID;
  logic WREADY;

  logic [3:0] BID;
  logic [1:0] BRESP;
  logic BVALID;
  logic BREADY;
endinterface

What about all the other signals (for example ARBURST,ARLOCK,ARCACHE,ARPROT,ARQOS,ARREGION)? There are many more signal according the specification of AXI4.

In addition are the following properties in the transaction are enough for write transaction?

typedef enum bit [3:0] { LENGTH_[1:16] } length_e;


class sequence_item extends uvm_sequence_item;
  rand bit [3:0] id;
  rand bit [31:0] address;
  rand length_e length;
  rand transfer transfers[];
  rand int unsigned delay;
endclass


class transfer extends uvm_sequence_item;
  rand bit[31:0] data;
  rand int unsigned delay;
endclass

Answer 1

此接口中的信号仅包含在固定大小和突发类型的AXI总线上执行单次写操作所需的最小信号集。如果您的DUT支持的不仅仅是简单的写入，那么您必须添加其他信号。例如，如果您想测试读取操作，则还必须添加读取地址通道和读取数据通道所需的所有信号。

只有当您知道您的设计不支持时，才能省略某些AXI信号。如果在写入操作中支持不同的突发类型，则必须将AWBURST信号添加到接口以及事务中。

creating test bench for AXI bus

1 个答案: