Question

我在vhdl中有一个4到16个解码器。我想提出一个启用输入，但我是vhdl编码的新手。我想保留代码的这种结构（我不想要任何其他快捷方式，或者完全改变代码）。我尝试为启用编写e输入，并尝试执行if e = "1" then但它无法正常工作。

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decode4to16 is
port(
oct : in std_logic_vector(3 downto 0);
e : in std_logic;
dec : out std_logic_vector(15 downto 0));
end decode4to16;
architecture arch of decode4to16 is
begin
if e = "1" then
with oct select
dec <=
"0000000000000001" when "0000",
"0000000000000010" when "0001",
"0000000000000100" when "0010",
"0000000000001000" when "0011",
"0000000000010000" when "0100",
"0000000000100000" when "0101",
"0000000001000000" when "0110",
"0000000010000000" when "0111",
"0000000100000000" when "1000",
"0000001000000000" when "1001",
"0000010000000000" when "1010",
"0000100000000000" when "1011",
"0001000000000000" when "1100",
"0010000000000000" when "1101",
"0100000000000000" when "1110",
"1000000000000000" when "1111",
"0000000000000000" when others;
end if;
end arch;

Answer 1

请在未来中使用适当的缩进，以便于阅读。

if语句只能在进程中使用，正如@Josh指出的那样， e 是 std_logic ，在验证或赋值时需要单引号。最终结果如下：

DECODER: process(e, oct) -- e and oct are in sensitivity list, which means output the process statements are executed whenever one of these change
begin
    if e = '1' then
        case oct is
            when "0000" => dec <= X"0001";
            when "0001" => dec <= X"0002";
            ...
            when others => dec <= X"0000";
        end case;
    end if;
end process DECODER;

另外，这将创建一个 latch ，因为有一个隐含的行为，即信号的值在未分配时不会改变。在这种情况下，当 e 为'0'时会发生这种情况;即你的陈述中没有其他内容。这可能不是你想要的，当 e 为'0'时，应该为 dec 赋值。

在解码器（VHDL）上启用使能输入

1 个答案: