Question

我正在尝试将实体的输出连接到另一个实体的输入。最终连接第三个实体将被连接，但我想了解将两个实体连接在一起的过程。

我是否使用端口映射？如果我这样做，是否将它们添加到不同实体的两个体系结构中以链接它们？

我知道它不会像下面那么简单：

link: transmitter port map (output_e1=>input_e2);

我试过这个但是使用指向组件声明的ModelSim返回错误！

更新

ENTITY transmitter is   
    port(  
        transmission : out  STD_LOGIC_VECTOR (31 downto 0)
    );  
end transmitter;        

architecture Behavioral of transmitter  is  
end Behavioral;  

Entity receiver is   
    PORT(  
        rxi:in signed (7 downto 0)
end receiver;  

architecture Behavioral of receiver is 
end Behavioral;

上述代码不包含所有说明和命令。我的程序有效，但我有两个实体，希望将它们链接在一个通信系统中。

Answer 1

请参见以下示例，使用两个半加法器完成的完整加法器电路。您可以看到前半部加法器输出如何连接作为第二半加法器的输入。

    --top module(full adder) entity declaration
entity fulladder is
    port (a : in std_logic;
            b : in std_logic;
           cin : in std_logic;
           sum : out std_logic;
           carry : out std_logic
         );
end fulladder;
--top module architecture declaration.
architecture behavior of fulladder is
--sub-module(half adder) is declared as a component before the keyword "begin".
   component halfadder
    port(
         a : in std_logic;
         b : in std_logic;
         sum : out std_logic;
         carry : out std_logic
        );
    end component;
--All the signals are declared here,which are not a part of the top module.
--These are temporary signals like 'wire' in Verilog.
signal s1,c1,c2 : std_logic:='0';

begin
--instantiate and do port map for the first half adder.
  HA1 : halfadder port map (
          a => a,
          b => b,
          sum => s1,
          carry => c1
        );
--instantiate and do port map for the second half adder.
 HA2 : halfadder port map (
          a => s1,
          b => cin,
         sum => sum,
         carry => c2
        );
carry <= c1 or c2;  --final carry calculation

end;

有关说明，请参阅此link。

将实体的输出链接到另一个实体的输入

更新

1 个答案: