Question

Verilog：不能由原始或连续的任务驱动

好吧，它在我执行FullAdder 32位实例的每一行上都给出了这个错误。

 module Multiplier_S(output reg [63:0] f_result, input [31:0] a, input [31:0] b);

   wire [31:0] sum1,sum2,sum3,sum4,sum5,sum6,sum7,sum8,sum9,sum10,sum11,sum12,sum13,sum14,
   sum15,sum16,sum17,sum18,sum19,sum20,sum21,sum22,sum23,sum24,sum25,sum26,sum27,sum28,
   sum29,sum30,sum31;

   wire [31:0] and1,and2,and3,and4,and5,and6,and7,and8,and9,and10,and11,and12,and13,and14,
   and15,and16,and17,and18,and19,and20,and21,and22,and23,and24,and25,and26,and27,and28,
   and29,and30,and31,and32;

   reg [63:0] result;


   //bit0
   AND_Bank a_1(and1, a[0], b);
   initial begin
   result[0] = and1[0];
   end
   Shift_Right_32bit shift1(and1, 1, and1);
   initial begin
   and1[31]=1'b0;
   end
   //bit 1
   AND_Bank a_2(and2, a[1], b);
   FullAdder_32bit adder1(sum1, result[1], and2, and1);
   //bit 2
   AND_Bank a_3(and3, a[2], b);
   FullAdder_32bit adder2(sum2, result[2], and3, sum1);
   //bit 3
   AND_Bank a_4(and4, a[3], b);
   FullAdder_32bit adder3(sum3, result[3], and4, sum2);
   //bit 4
   AND_Bank a_5(and5, a[4], b);
   FullAdder_32bit adder4(sum4, result[4], and5, sum3);
   //bit 5
   AND_Bank a_6(and6, a[5], b);
   FullAdder_32bit adder5(sum5, result[5], and6, sum4);
   //bit 6
   AND_Bank a_7(and7, a[6], b);
   FullAdder_32bit adder6(sum6, result[6], and7, sum5);
   //bit 7
   AND_Bank a_8(and8, a[7], b);
   FullAdder_32bit adder7(sum7, result[7], and8, sum6);
   //bit 8
   AND_Bank a_9(and10, a[8], b);
   FullAdder_32bit adder8(sum8, result[8], and9, sum7);
   //bit 9
   AND_Bank a_10(and11, a[9], b);
   FullAdder_32bit adder9(sum9, result[9], and10, sum8);
   //bit 10
   AND_Bank a_11(and12, a[10], b);
   FullAdder_32bit adder10(sum10, result[10], and11, sum9);
   //bit 11
   AND_Bank a_12(and13, a[11], b);
   FullAdder_32bit adder11(sum11, result[11], and12, sum10);
   //bit 12
   AND_Bank a_13(and14, a[12], b);
   FullAdder_32bit adder12(sum12, result[12], and13, sum11);
   //bit 13
   AND_Bank a_14(and15, a[13], b);
   FullAdder_32bit adder13(sum13, result[13], and14, sum12);
   //bit 14
   AND_Bank a_15(and16, a[14], b);
   FullAdder_32bit adder14(sum14, result[14], and15, sum13);
   //bit 15
   AND_Bank a_16(and17, a[15], b);
   FullAdder_32bit adder15(sum15, result[15], and16, sum14);
   //bit 16
   AND_Bank a_17(and18, a[16], b);
   FullAdder_32bit adder16(sum16, result[16], and17, sum15);
   //bit 17
   AND_Bank a_18(and19, a[17], b);
   FullAdder_32bit adder17(sum17, result[17], and18, sum16);
   //bit 18
   AND_Bank a_19(and20, a[18], b);
   FullAdder_32bit adder18(sum18, result[18], and19, sum17);
   //bit 19
   AND_Bank a_20(and21, a[19], b);
   FullAdder_32bit adder19(sum19, result[19], and20, sum18);
   //bit 20
   AND_Bank a_21(and22, a[20], b);
   FullAdder_32bit adder20(sum20, result[20], and21, sum19);
   //bit 21
   AND_Bank a_22(and23, a[21], b);
   FullAdder_32bit adder21(sum21, result[21], and22, sum20);
   //bit 22
   AND_Bank a_23(and24, a[22], b);
   FullAdder_32bit adder22(sum22, result[22], and23, sum21);
   //bit 23
   AND_Bank a_24(and25, a[23], b);
   FullAdder_32bit adder23(sum23, result[23], and24, sum22);
   //bit 24
   AND_Bank a_25(and25, a[24], b);
   FullAdder_32bit adder24(sum24, result[24], and25, sum23);
   //bit 25
   AND_Bank a_26(and26, a[25], b);
   FullAdder_32bit adder25(sum25, result[25], and26, sum24);
   //bit 26
   AND_Bank a_27(and27, a[26], b);
   FullAdder_32bit adder26(sum26, result[26], and27, sum25);
   //bit 27
   AND_Bank a_28(and28, a[27], b);
   FullAdder_32bit adder27(sum27, result[27], and28, sum26);
   //bit 28
   AND_Bank a_29(and29, a[28], b);
   FullAdder_32bit adder28(sum28, result[28], and29, sum27);
   //bit 29
   AND_Bank a_30(and30, a[29], b);
   FullAdder_32bit adder29(sum29, result[29], and30, sum28);
   //bit 30
   AND_Bank a_31(and31, a[30], b);
   FullAdder_32bit adder30(sum30, result[30], and31, sum29);
   //bit 31
   AND_Bank a_32(and32, a[31], b);
   FullAdder_32bit adder31(sum31, result[31], and32, sum30);

   //bit 63 al 32
   initial begin
   result[62:32] = sum31[30:0];
   end

   if(a[31] || b[31])
      begin
      initial begin
         result[63] = 1'b0;
      end
      end

   else
   begin
   initial begin
    result[63] = 1'b1;
   end
   end
   initial begin
   f_result[63:0] = result[31:0];
   end
endmodule

这是完整的加法器模块：

module FullAdder_32bit(output [31:0] result, output reg carry, input [31:0] a, input [31:0] b);
   reg [32:0] temp_sum;

   initial begin
   temp_sum = a + b;
   checkCarryFlag;
   assign result = temp_sum[31:0];
   end

   task checkCarryFlag;
        begin   
           if( temp_sum[32] == 1 )
            begin
            carry = 1;
            end 
           else carry = 0;
        end
     endtask

endmodule

这里是一个错误的命令控制台，但它确实是每次我调用全加器时。我是verilog的初学者，并希望了解为什么我会收到所有这些错误。提前谢谢。

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Answer 1

连接模块时，实例的输出必须驱动电线。

例如

module top

  wire block_wire_output;

  block u_block( 
    .block_reg_output( block_wire_output)
  );
endmodule

module block(
  output reg block_reg_output
);

initial begin
   block_reg_output =1'b1;
end
endmodule

在您的代码中，reg [63:0] result;由实例的输出端口驱动。这违反了上述规则，结果应声明为导线（wire [63:0] result;）。这意味着您无法在initial或always块中定义部分结果。您对initial的使用看起来不正确，因为它们只被评估一次。看起来你真的想用：

 assign result[0] = and1[0];

Verilog：不能由原语或连续赋值驱动

1 个答案: