Question

你好我想完成这件事

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我写了这段代码，是不是正确？因为我在MAX + PLUS II上的编译器没有显示任何错误......

LIBRARY IEEE;
USE IEE.STD_LOGIC_1164.ALL;

ENTITY alarm IS PORT
(ON/OFF,MOTION_SENSOR,.LIGHT_SENSOR,.SOUND_SENSOR,.CAMERA_SENSOR,.IP_SENSOR,.TEMPERATURE_SENSOR: IN STD_LOGIC;
SENSOR_SIRINE,SENSOR_LIGHT:OUT STD_LOGIC);
END alarm;

ARCHITECTURE LEITOURGEIA OF alarm IS
BEGIN
if (ON/OFF='1' AND (MOTION_SENSOR='1' OR LIGHT_SENSOR='1' OR SOUND_SENSOR='1' OR CAMERA_SENSOR='1' OR IP_SENSOR='1' OR TEMPERATURE_SENSOR='1')) then
SENSOR_LIGHT<='1';
SENSOR_SIRINE<='1';

ELSE IF (ON/OFF='0' AND (MOTION_SENSOR='1' OR LIGHT_SENSOR='1' OR SOUND_SENSOR='1' OR CAMERA_SENSOR='1' OR IP_SENSOR='1' OR TEMPERATURE_SENSOR='1')) then
SENSOR_LIGHT<='1';
SENSOR_SIRINE<='0';

ELSE
SENSOR_LIGHT<='0';
SENSOR_SIRINE<='0';

END IF

END LEITOURGEIA;

Answer 1

这是您的代码看起来像有效VHDL的近似值：

library ieee;
use ieee.std_logic_1164.all;

entity alarm is 
    port (
        on_off, motion_sensor, light_sensor,
        sound_sensor, camera_sensor, ip_sensor, 
        temperature_sensor:           in  std_logic;
        sensor_sirine, sensor_light:  out std_logic
    );
end alarm;

architecture leitourgeia of alarm is
begin
unlabelled:
    process (on_off, motion_sensor, light_sensor, sound_sensor, 
             camera_sensor, ip_sensor, temperature_sensor)
    begin
        if on_off = '1' and 
            (motion_sensor = '1' or light_sensor = '1' or sound_sensor = '1' or
             camera_sensor = '1' or ip_sensor = '1' or temperature_sensor='1') then
            sensor_light <= '1';
            sensor_sirine <= '1';
        elsif on_off = '0' and 
            (motion_sensor = '1' or light_sensor = '1' or sound_sensor = '1' or 
            camera_sensor = '1' or ip_sensor = '1' or temperature_sensor = '1') then
            sensor_light <= '1';
            sensor_sirine <= '0';
        else
            sensor_light <= '0';
            sensor_sirine <= '0';
        end if;
    end process;
end leitourgeia;

我缩进了它，修正了一些拼写错误，制作了有效的标识符，将if语句放在一个进程中并使else if成为elsif，再加上摆脱两组多余的括号。 / p>

现在分析，阐述和模拟。

这种架构也是如此：

architecture foo of alarm is
    signal alarm_light: std_logic; 
begin
    alarm_light <= motion_sensor or sound_sensor or light_sensor or 
                   camera_sensor or ip_sensor or temperature_sensor;

    sensor_light <= alarm_light;

    sensor_sirine <= '1' when alarm_light = '1'  and on_off = '1' else
                     '0'; 
end architecture foo;

更接近于引用的原理图图像。

这个更接近于引用的原理图：

architecture fum of alarm is
    signal alarm_light: std_logic;
begin
    alarm_light <= motion_sensor or sound_sensor or light_sensor or 
                   camera_sensor or ip_sensor or temperature_sensor;

    sensor_light <= alarm_light;

    sensor_sirine <= on_off and alarm_light;
end architecture fum;

VHDL-切换正确的代码

1 个答案: