Question

我使用VHDL创建了一个位序列检测器（用于序列1110）。我用摩尔的状态机来完成任务。

我能够编译我的代码并获得所需的输出。

但是在FPGA板上我应该使用SW0作为时钟，SW1作为数据输入，SW2作为RESET，任何LED作为数据输出。

我面临的问题：

我无法将时钟信号分配给交换机，我总是收到错误。所以我将时钟信号分配给电路板上的默认时钟信号，即LOC =“E3”它工作正常。但根据我的问题，我需要将它分配给一个开关。怎么办？
我无法在fpga板上显示输出，即一旦应用了引脚数据，LED就会以肉眼快速亮起。关于如何根据上述问题使用3输入开关和LED作为输出显示输出的任何建议？

以下代码是我的设计实现：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Design is

    Port ( clock : in STD_LOGIC;
           din : in STD_LOGIC;
           rst : in STD_LOGIC;
           dout : out STD_LOGIC);
end Design;

architecture Behavioral of Design is

type state is (st0, st1, st2, st3, st4);
signal present_state, next_state : state;
begin

synchronous_process: process (clock)

begin
if rising_edge(clock) then
if (rst = '1') then
present_state <= st0;
else
present_state <= next_state;
end if;
end if;
end process;

output_decoder : process(present_state, din)
begin
next_state <= st0;

case (present_state) is

when st0 =>
if (din = '1') then
next_state <= st1;
else
next_state <= st0;
end if;

when st1 =>
if (din = '1') then
next_state <= st2;
else
next_state <= st0;
end if;

when st2 =>
if (din = '1') then
next_state <= st3;
else
next_state <= st0;
end if;

when st3 =>
if (din = '1') then
next_state <= st3;
else
next_state <= st4;
end if;

when st4 =>
if (din = '1') then
next_state <= st1;
else
next_state <= st0;
end if;

when others =>
next_state <= st0;
end case;
end process;

next_state_decoder : process(present_state)
begin
case (present_state) is

when st0 =>

dout <= '0';
when st1 =>
dout <= '0';
when st2 =>
dout <= '0';
when st3 =>
dout <= '0';
when st4 =>
dout <= '1';
when others =>
dout <= '0';
end case;

end process;

end Behavioral;

以下是我的测试平台：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_moore is
end tb_moore;

architecture Behavioral of tb_moore is

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT Design
PORT(
clock : IN std_logic;
din : IN std_logic;
rst : IN std_logic;
dout : OUT std_logic
);
END COMPONENT;

--Inputs
signal clock : std_logic := '0';
signal din : std_logic := '0';
signal rst : std_logic := '0';

--Outputs
signal dout : std_logic;

-- Clock period definitions
constant clk_period : time := 20 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: Design PORT MAP (
clock => clock,
din => din,
rst => rst,
dout => dout
);

-- Clock process definitions
clk_process :process
begin
clock <= '0';
wait for clk_period/2;
clock <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin

rst <= '1';

wait for 20 ns;

rst <= '0';

din <= '1';

wait for 20 ns;

din <= '1';

wait for 20 ns;

din <= '1';

wait for 20 ns;

din <= '1';

wait for 20 ns;

din <= '1';

wait for 20 ns;

din <= '0';

wait for 20 ns;

din <= '1';

wait for 20 ns;

din <= '1';

end process;

END;

以下是我用于Nexys DDR4 FPGA板的约束文件。

## Clock signal
NET "clock"   LOC = "E3"    | IOSTANDARD = "LVCMOS33";  

## Switches
NET "din"          LOC=L16 | IOSTANDARD=LVCMOS33; 
NET "rst"          LOC=M13 | IOSTANDARD=LVCMOS33; 

## LEDs
NET "dout"         LOC=H17 | IOSTANDARD=LVCMOS33;

使用3个输入开关在FPGA上输出序列检测器

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