正确嵌套if语句

Question

我正在为8x8乘法器编写一些代码。我正在使用嵌套的if语句。使用以下代码，当a = x“ 02”的条件为true时，则输出c变得不确定（U）。

1）我的嵌套if语句正确吗？

2）嵌套期间我的代码中是否有语法错误？

entity mul is
Port ( 
       a : in  STD_LOGIC_VECTOR (7 downto 0);
       b : in  STD_LOGIC_VECTOR (7 downto 0);
       c : out STD_LOGIC_VECTOR (7 downto 0)
);
end mul;

architecture Behavioral of mul is
    signal s1,s2: STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
    process(b)
    begin
        s2 <= x"1B";
        if a = x"01" then
            c <= b;
-- ERROR OCCURING HERE
        elsif a = x"02" then
            if b(7) = '1' then
                s1(7) <= b(6);
                s1(6) <= b(5);
                s1(5) <= b(4);
                s1(4) <= b(3);
                s1(3) <= b(2);
                s1(2) <= b(1);
                s1(1) <= b(0);
                s1(0) <= '0';
                c <= s1 xor s2;
            else 
                s1(7) <= b(6);
                s1(6) <= b(5);
                s1(5) <= b(4);
                s1(4) <= b(3);
                s1(3) <= b(2);
                s1(2) <= b(1);
                s1(1) <= b(0);
                s1(0) <= '0';
                c <= s1;
            end if;
        elsif a = x"03" then
            if b(7) = '1' then
                s1(7) <= b(6);
                s1(6) <= b(5);
                s1(5) <= b(4);
                s1(4) <= b(3);
                s1(3) <= b(2);
                s1(2) <= b(1);
                s1(1) <= b(0);
                s1(0) <= '0';
                c <= (s1 xor s2) xor b;
            else 
                s1(7) <= b(6);
                s1(6) <= b(5);
                s1(5) <= b(4);
                s1(4) <= b(3);
                s1(3) <= b(2);
                s1(2) <= b(1);
                s1(1) <= b(0);
                s1(0) <= '0';
                c <= s1 xor b;
            end if;
        end if;
    end process;
end Behavioral;