Question

我了！

我写了一些简单的东西，以展示实体如何融合在一起。但是，我无法弄清楚为什么组合实体的输出永远不会假定任何值（U除外）。这是代码（它非常简单，我保证！）

library ieee;
use ieee.std_logic_1164.all;

entity OR_LOGIC is
    port(
        in_a  : in  std_logic;
        in_b  : in  std_logic;
        out_c : out std_logic
    );
end entity;

architecture OR_LOGIC_ARCH of OR_LOGIC is
begin
    out_c <= in_a or in_b;
end OR_LOGIC_ARCH;


library ieee;
use ieee.std_logic_1164.all;

entity AND_LOGIC is
    port(
        in_a  : in  std_logic;
        in_b  : in  std_logic;
        out_c : out std_logic
    );
end entity;

architecture AND_LOGIC_ARCH of AND_LOGIC is
begin
    out_c <= in_a and in_b;
end AND_LOGIC_ARCH;


library ieee;
use ieee.std_logic_1164.all;

entity COMBO is
    port(
        in_a  : in  std_logic;
        in_b  : in  std_logic;
        in_c  : in  std_logic;
        out_d : out std_logic
    );
end entity;

architecture COMBO_ARCH of COMBO is
    signal wire1 : std_logic;
    signal wire2 : std_logic;
    component OR_LOGIC
        port(
            in_a  : in  std_logic;
            in_b  : in  std_logic;
            out_c : out std_logic
        );
    end component;
    component AND_LOGIC
        port(
            in_a  : in  std_logic;
            in_b  : in  std_logic;
            out_c : out std_logic
        );
    end component;
begin

    or1 : OR_LOGIC port map (in_a, in_b, wire1);
    and1 : AND_LOGIC port map(in_c, wire1, wire2);
end COMBO_ARCH;

然后：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity TEST_ENTITY is
end entity TEST_ENTITY;

architecture TEST_ENTITY_ARCH of TEST_ENTITY is    
    component ANDandOR
        port(
            in_a  : in  std_logic;
            in_b  : in  std_logic;
            in_c  : in  std_logic;
            out_d : out std_logic
        );
    end component; 
    signal in_a, in_b, in_c, out_d : std_logic;

begin

    combination : ANDandOR port map (in_a, in_b, in_c, out_d);

    process
    begin
        in_a <= '0';
        in_b <= '0';
        in_c <= '0';
        wait for 5ns;

        in_a <= '1';
        in_b <= '0';
        in_c <= '1';
        wait for 5ns;

        in_a <= '0';
        in_b <= '1';
        in_c <= '0';
        wait for 5ns;
    end process;

end architecture TEST_ENTITY_ARCH;

Answer 1

首先，您已将AND门的输出分配给wire2，但wire2处于浮动状态。您应该将它分配给您的输出

out_d <= wire2;

或从内部信号中删除wire2并直接分配输出。

and1 : AND_LOGIC port map(in_c, wire1, out_d);

其次，您的测试平台需要具有组件COMBO的正确名称才能正确映射。 Quartus可以为您生成测试平台模板，然后您可以向其添加测试代码。

处理 - ＆gt;开始 - ＆gt;启动测试台模板编写器

它非常方便：）

VHDL：组合实体（组件）的麻烦

1 个答案: