我想将2个组件(trng和wb_master_switch_2x)连接在一起。但是我从模拟中得到了一个错误,
错误:[XSIM 43-3249]未解决的信号“ wb_core4”被多重驱动。
我不是要从多个进程发出信号,但是为什么会出现此错误?
下面给出了相应的代码。
最诚挚的问候
type wb_bus_t is record
adr : std_ulogic_vector(31 downto 0); -- address
di : std_ulogic_vector(31 downto 0); -- slave input data
do : std_ulogic_vector(31 downto 0); -- slave output data (7 downto 0)
we : std_ulogic; -- write enable
--sel : std_ulogic_vector(03 downto 0); -- byte enable
stb : std_ulogic; -- strobe
cyc : std_ulogic; -- valid cycle
ack : std_ulogic; -- transfer acknowledge
end record;
signal wb_core4 : wb_bus_t;
component trngs
generic (
NUM_OSCILLATORS : natural-- number of XORed oscillators
);
port (
-- gloabl control --
clk_i_trng : in std_ulogic;
rst_i_trng : in std_ulogic;
-- 32-bit wishbone interface --
wb_dat_o_trng : out std_ulogic_vector(31 downto 0); -- read data
wb_dat_i_trng : in std_ulogic_vector(31 downto 0); -- write data
wb_we_i_trng : in std_ulogic; -- read/write
wb_stb_i_trng : in std_ulogic; -- strobe
wb_cyc_i_trng : in std_ulogic; -- valid cycle
wb_ack_o_trng : out std_ulogic; -- transfer acknowledge
wb_adr_i_trng : in std_ulogic_vector(31 downto 0)
);
component wb_master_switch_2x
port(
wb_clk_i : in std_ulogic;
wb_rstn_i : in std_ulogic;
-- wishbone slave port --
wb_slave_cyc_o : out std_ulogic; -- valid cycle
wb_slave_stb_o : out std_ulogic; -- valid strobe
wb_slave_we_o : out std_ulogic; -- write enable
--wb_slave_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
wb_slave_addr_o : out std_ulogic_vector(31 downto 0); -- access address
wb_slave_data_o : out std_ulogic_vector(31 downto 0); -- write data
wb_slave_data_i : in std_ulogic_vector(31 downto 0); -- read data
wb_slave_ack_i : in std_ulogic -- acknowledge
);
end component wb_master_switch_2x;
TRNG: trngs
generic map(NUM_OSCILLATORS => 1
)
port map(
-- gloabl control --
clk_i_trng => clk_int,
rst_i_trng => rst_int,
-- 32-bit wishbone interface --
wb_dat_o_trng => wb_core4.di,
wb_dat_i_trng => wb_core4.do,
wb_we_i_trng => wb_core4.we,
wb_stb_i_trng => wb_core4.stb,
wb_cyc_i_trng => wb_core4.cyc,
wb_ack_o_trng => wb_core4.ack,
wb_adr_i_trng => wb_core4.adr
);
switch_0: wb_master_switch_2x
port map(
wb_clk_i => clk_int,
wb_rstn_i => rst_int,
-- wishbone slave port --
wb_slave_cyc_o => wb_core4.cyc,
wb_slave_stb_o => wb_core4.stb,
wb_slave_we_o => wb_core4.we,
--wb_slave_sel_o => wb_core4.sel,
wb_slave_addr_o => wb_core4.adr,
wb_slave_data_o => wb_core4.do,
wb_slave_data_i => wb_core4.di,
wb_slave_ack_i => wb_core4.ack
);