我正在使用Quartus II，我需要在128x1B的8个组件中创建一个256 x 4B（1KB）的内存，但我不是vhdl的初学者。
这是使用MegaWizard Quartus II插件创建的128x1B组件（这不是问题所在）：
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY RAM_128B_MegaWizard IS
PORT
(
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END RAM_128B_MegaWizard;
ARCHITECTURE SYN OF ram_128b_megawizard IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 128,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 7,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;
现在问题就在于此。我正在尝试使用端口映射来实例化内存组件，我收到以下错误
Error (10500): VHDL syntax error at RAM_256x4B.vhd(50) near text "1.1"; expecting "end", or "(", or an identifier, or a concurrent statement
Error (10500): VHDL syntax error at RAM_256x4B.vhd(51) near text ";"; expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(53) near text ";"; expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(55) near text ";"; expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(57) near text ";"; expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(60) near text ";"; expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(62) near text ";"; expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(64) near text ";"; expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(66) near text ";"; expecting "<="
这是代码。我的地址必须是10位大小，我正在使用解码器和多路复用器。
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.RAM_128B_MegaWizard_package.all;
use work.dec1to2_package.all;
use work.mux2to1_package.all;
entity RAM_256x4B is
generic(
depth : integer range 1 to 10 := 10;
width: integer range 1 to 32 := 32;
init_file : string := "init_file2.mif");
-- .mif filename
port(Clock : in std_logic;
WrEn: in std_logic;
-- write control signal
Address : in std_logic_vector(depth-1 downto 0);
-- read and write addresses
data : in std_logic_vector(width-1 downto 0);
-- data to be written
DataOut : out std_logic_vector(width-1 downto 0));
-- memory read output
end RAM_256x4B;
architecture behavior of RAM_256x4B is
signal dOut0: std_logic_vector(width-1 downto 0);
signal dOut1: std_logic_vector(width-1 downto 0);
signal En: std_logic_vector(0 to 1);
begin
decoder: dec1to2 port map (Address(depth-3), WrEn, En);
1.1: RAM_128B_MegaWizard port map
(Clock, En(0), Address(depth-4 downto 0), data(width-1 downto 24), dOut0(width-1 downto 24));
1.2: RAM_128B_MegaWizard port map
(Clock, En(0), Address(depth-4 downto 0), data(23 downto 16), dOut0(23 downto 16));
1.3: RAM_128B_MegaWizard port map
(Clock, En(0), Address(depth-4 downto 0), data(15 downto 8), dOut0(15 downto 8));
1.4: RAM_128B_MegaWizard port map
(Clock, En(0), Address(depth-4 downto 0), data(7 downto 0), dOut0(7 downto 0));
2.1: RAM_128B_MegaWizard port map
(Clock, En(1), Address(depth-4 downto 0), data(width-1 downto 24), dOut1(width-1 downto 24));
2.2: RAM_128B_MegaWizard port map
(Clock, En(1), Address(depth-4 downto 0), data(23 downto 16), dOut1(23 downto 16));
2.3: RAM_128B_MegaWizard port map
(Clock, En(1), Address(depth-4 downto 0), data(15 downto 8), dOut1(15 downto 8));
2.4: RAM_128B_MegaWizard port map
(Clock, En(1), Address(depth-4 downto 0), data(7 downto 0), dOut1(7 downto 0));
mux: mux2to1 port map (dOut0, dOut1, Address(depth-3),DataOut);
end behavior;
我知道它不完整，但无论我做什么编译都会给我带来同样的错误。即使开始和结束架构之后的部分只是
1.1: RAM_128B_MegaWizard port map
(Clock, En(0), Address(depth-4 downto 0), data(width-1 downto 24), dOut0(width-1 downto 24));
同样会发生。
我理解端口映射不能在进程内使用，但是有进程的组件（128x1B）也不能进行端口映射？我如何结合这些组件来制作我想要的东西？
答案 0 :(得分：1)
我认为您在通过引用进行端口映射时遇到问题。这是您实例化的组件：
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
因此，如果您通过引用进行操作，则应该进行此实例化：
inst_1_1 : RAM_128B_MegaWizard port map
(Address(depth-4 downto 0), Clock, data(width-1 downto 24), En(0), dOut0(width-1 downto 24));
注意信号的放置。这就是为什么我更喜欢做显式端口映射，你会减少错误。
此外，我不确定对您的实例化名称有什么限制，但1.1对我来说似乎不是一个好名字。尝试以字母开头并且只有下划线而不是句号的东西。
答案 1 :(得分：0)
标签必须是标识符。这些导致错误（10500）VHDL ...错误。
基本标识符：
basic_identifier ::=
letter { [ underline ] letter_or_digit }
letter_or_digit ::= letter | digit
letter ::= upper_case_letter | lower_case_letter
或扩展标识符：
extended_identifier ::=
\ graphic_character { graphic_character } \
在你的情况下，标签（1.1,1.2等）需要以一个字母开头，有点像Russel在他的答案中偶然演示，并且除了在实例化它们的端口接口中的错误位置关联之外。 / p>
解决这两个问题。