Question

我想实现3xor门，前两个xor门的输出应该是最后xor门的输入

xor1--->
             xor3----> final output
xor2--->

这是我的代码，我不确定到目前为止我所做的事情是否正常，我想我必须宣布这个拱门。当我做mod。 thingys？干杯求救！

 library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    architecture struct of triplexor is
    component unit10
    port (a0, a1: in bit; o1: out bit); --xor1
    end component;
    architecture func of unit10 is 
    begin
       o1 <= a0 xor a1;
    end func;
    component unit11
    port (a2, a3: in bit; o2: out bit); --xor2
    end component;
    architecture func of unit11 is 
    begin
       o2 <= a2 xor a3;
    end func;
    component unit2
    port (i1, i2: in bit; yi: out bit); --xor3
    end component;
    architecture func of unit2 is 
    begin
       yi <= i1 xor i2;
    end func;
    signal ya, yb, yout: bit;

    begin
    mod_unit10: unit10 port map (a, b, ya);
    mod_unit11: unit11 port map (a, b, yb);
    mod_unit2 : unit2 port map (ya, yb, yout);
    output: y<=yout; 
    end architecture struct;

Answer 1

这是您的代码，只有3个相同组件的实例：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity triplexor ...
end entity;

architecture struct of triplexor is
  component myXor
    port (
      i0, i0: in  bit;
      o:      out bit
    );
  end component;

  architecture rtl of myXor is 
  begin
    o <= i0 xor i1;
  end rtl;

  signal ya, yb, yout: bit;

begin
  -- using port mapping by position
  inst_xor1: myXor
    port map (
      a, b,
      ya
    );

  inst_xor2: myXor
    port map (
      a, b,
      yb
    );

  -- using port mapping by name (I prefer this style - it's safer if someone changes a port list)
  inst_xor3: myXor
    port map (
      i0 => ya,
      i1 => yb,
      o =>  yout
    );

  y <= yout; 
end architecture struct;

VHDL 3xor使用struct进行门控

1 个答案: