我正在寻找一种分配std_(u)logic_vector的好方法,而无需手动添加零,如下面的代码所示。示例代码:
signal test_32 : std_ulogic_vector(31 downto 0);
signal test_14 : std_ulogic_vector(13 downto 0);
test_32 <= "000000000000000000" & test_14; -- This works fine of course
我当然可以:
test_32(13 downto 0) <= test_14;
test_32(31 downto 14) <= (others => '0');
我想到了这样的东西(将所有内容放在一行中) 但这不起作用:
test_32 <= (13 downto 0 => test_14, others => '0');
如果最低的14位也保持不变,则上面的代码有效:
test_32 <= (13 downto 0 => '1', others => '0');
有人建议吗?