Question

特定实体的输出取决于它在矢量和所有输入中的位置。实现这个的最简单方法似乎是for循环中的for循环。但是，Quartus II 13.0sp1在第二个for循环中失败：

VHDL syntax error at mcve.vhd(24) near text "IN"; expecting "(", or "'", or "."

我可能搞砸了语法，但我确信VHDL能够在循环中循环。

for-loop中for循环的正确实现是什么？这是我到目前为止所做的。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

TYPE ANAT_SLV16 IS ARRAY ( NATURAL RANGE <> ) OF STD_LOGIC_VECTOR( 15 DOWNTO 0 );

ENTITY mcve IS
    GENERIC(
        PORTS  : POSITIVE := 256;
        HPORTS : POSITIVE := 128
    );
PORT(
    X : IN  ANAT_SLV16( PORTS - 1 DOWNTO 0 );
    Y : OUT ANAT_SLV16( HPORTS - 1 DOWNTO 0 );
    );
END mcve;

ARCHITECTURE loops OF mcve IS
    SIGNAL to_Y : ANAT_SLV16( HPORTS - 1 DOWNTO 0 ) := (others -> '0');
BEGIN

    gen : FOR i IN 0 TO HPORTS - 1 GENERATE
        FOR j IN 0 TO PORTS - 1 GENERATE -- error near text "IN"; expecting "(", or "'", or "."
            to_Y(( i )) <= to_Y(( i )) + X( j );
        END GENERATE;
    END GENERATE;

    Y <= to_Y;

END loops;

Answer 1

那些不是FOR循环。它们是FOR..GENERATE语句，每个语句都需要自己的标签。

gen : FOR i IN 0 TO HPORTS - 1 GENERATE
    gen2: FOR j IN 0 TO PORTS - 1 GENERATE
        to_Y(( i )) <= to_Y(( i )) + X( j );
    END GENERATE;
END GENERATE;

我希望您对这将产生的硬件大小有一个良好的感觉。

For-loop在另一个for循环VHDL中

1 个答案: