vhdl编码新手,目前正试图在clk_out出现下降时编写代码, cs将是' 0' 0在经历clk_out下降沿后的设定持续时间内,不会受到包括clk_out在内的任何其他条件的影响, 然后回到' 1'过了一会儿。
HDLCompilet:806 syntax error near " loop " / " if " " ;" ( on END)
测试台代码
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clk200Hz_tb IS
END clk200Hz_tb;
ARCHITECTURE behavior OF clk200Hz_tb IS
COMPONENT clk200Hz
PORT(
clk_in : IN std_logic;
reset : IN std_logic;
clk_out: OUT std_logic;
cs : IN std_logic
);
END COMPONENT;
-- Inputs
signal clk_in : std_logic := '0';
signal reset : std_logic := '0';
signal cs : std_logic := '1' ;
-- Outputs
signal clk_out : std_logic ;
constant clk_in_t : time := 20 ns;
BEGIN
-- Instance of unit under test.
uut: clk200Hz PORT MAP (
clk_in => clk_in,
reset => reset,
clk_out => clk_out,
cs => cs
);
-- Clock definition.
entrada_process :process
begin
clk_in <= '0';
wait for clk_in_t / 2;
clk_in <= '1';
wait for clk_in_t / 2;
end process;
-- Processing.
stimuli: process
begin
reset <= '1'; -- Initial conditions.
wait for 100 ns;
reset <= '0'; -- Down to work!
wait;
end process;
** -- cs proceesing .
cs_process: process
begin
if falling_edge(clk_out) then
for i in 0 to 50 loop
cs <= '0';
if ( i =40 ) then
cs <= '1';
end loop;
else
cs <='1';
end if;
end loop;
**
END;
behavioral code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk200Hz is
Port (
clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out: out STD_LOGIC;
cs : in STD_LOGIC
);
end clk200Hz;
architecture Behavioral of clk200Hz is
signal temporal: STD_LOGIC;
signal counter : integer range 0 to 124999 := 0;
begin
frequency_divider: process (reset, clk_in) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (counter = 124999) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral;