Question

我对使用aux映射clock_div_1hz_aux感到困惑。我需要映射这两个端口（aux与clock_div_1hz_aux），我不知道如何。正如我在image

中所描述的那样映射了所有其他的

enter image description here

以下是我使用的代码：

entity controler is
Port ( reset : in STD_LOGIC;
clock : in STD_LOGIC;
....................
);
end controler;

component numarator
 Port (
 clk_num : in std_logic;
 reset_num : in std_logic;
 count : out std_logic_vector (3 downto 0)
 );
 end component;

 component div_num
 Port (
 clock_div: in std_logic;
 reset_div : in std_logic;
 clock_div_1hz: buffer std_logic;
 clock_bla : out std_logic
 );
 end component;

num1: div_num PORT MAP(
 clock_div=>clock,
 clock_div_1hz => clk1hz,
 reset_div => reset

 );

num2: numarator PORT MAP(
 clk_num =>clk1hz,
 reset_num =>reset,
 count=>sensor_count
 );

谢谢！

Answer 1

为避免在组件（div_num）中使用缓冲区，可以将缓冲区声明为输出参数，并将中间信号添加到（div_num）的体系结构中。只需使用设计中的中间信号，并将其作为并发语句分配给输出参数。例如（div_num的架构）：

architecture ... of ... is
begin
   output_parameter <= intermediate_parameter;
   process(...)
   begin
       -- use the intermediate_paramter instead of output_parameter
   end process;
end architecture;

经过上述修改：看来你有3个组件（div_num，numerator，controler）。

如果要将输出参数（clock_div_1hz_aux）连接到（aux），只需声明一个接口信号（clk1hz_aux）并将其添加到组件（div_num和controler）。

例如：

signal clk1hz_aux : std_logic;
component div_num
    Port(
        clock_div         : in  std_logic;
        reset_div         : in  std_logic;
        clock_div_1hz     : out std_logic;
        clock_div_1hz_aux : out std_logic
    );
end component;
component numarator
    Port(
        clk_num   : in  std_logic;
        reset_num : in  std_logic;
        count     : out std_logic_vector (3 downto 0)
    );
end component;
component controler
    Port(
        clock : in std_logic;
        count : in std_logic_vector (3 downto 0)
        aux   : in std_logic;
        reset : in std_logic;
        -- declare output parameters of controler block
    );
end component;
num1 : div_num   PORT MAP(clock,reset,clk1hz,clk1hz_aux);
num2 : numarator PORT MAP(clk1hz,reset,sensor_count);
cntr : controler PORT MAP(clock,sensor_count,clk1hz_aux,reset,....);

Answer 2

Amir，不能使用这种类型的映射吗？

entity mapare is

Port ( 

     reset : in  STD_LOGIC;
     clock : in  STD_LOGIC;
     aux : in std_logic;
     ...........
    );
end mapare;


architecture Behavioral of mapare is

    component numarator is
        Port (
                clk_num : in std_logic;
                reset_num : in std_logic;
                count : out std_logic_vector (3 downto 0)
                );
    end component;      

    component div_num is
        Port (
                clock_div: in std_logic;
                reset_div : in std_logic;
                clock_div_1hz: out std_logic;
                clock_div_1hz_aux: out std_logic

              );
        end component;  

    component controler is
        Port (
                clock: in std_logic;
                reset: in std_logic;
                aux : in std_logic;
                ...........
        );
        end component;  

signal sensor_count : STD_LOGIC_VECTOR (3 downto 0);
signal clk1hz: std_logic := '0';
signal aux1 : std_logic ;


begin
num1: div_num PORT MAP(
            clock_div=>clock,
            clock_div_1hz => clk1hz,
            reset_div => reset,
            clock_div_1hz_aux => aux1

            );

num2: numarator PORT MAP(
            clk_num =>clk1hz,
            reset_num =>reset,
            count=>sensor_count
            );


num3: controler PORT MAP (
         reset => reset,
         clock => clock,
         ...........
         aux=> aux1

        );

end Behavioral;

在VHDL中映射缓冲区端口

2 个答案: