为什么此移位寄存器无法在VHDL中正确加载？

Question

我有一个定制设计的移位寄存器，输入DL（最左边的输入），DR（最右边），CLR清除和加载DR，S向右移动，W加载到最左边。在测试之后，最右边的是正在加载而不是左边。我已多次重读代码，但我无法弄清楚出了什么问题。这是代码：

    library IEEE;
use IEEE.std_logic_1164.all;

entity shiftregister is
    port (
        CLK, CLR: in STD_LOGIC;
        S: in STD_LOGIC; --Shift right
 W: in STD_LOGIC; --Write
 Cin: in STD_LOGIC; --possible carry in from the addition
        DL: in STD_LOGIC_VECTOR (7 downto 0); --left load for addition result
 DR: in STD_LOGIC_VECTOR (7 downto 0); --right load for initial multiplier
        Q: out STD_LOGIC_VECTOR (15 downto 0)
     );
end shiftregister ;

architecture shiftregister of shiftregister is
signal IQ: std_logic_vector(15 downto 0):= (others => '0');
begin
   process (CLK)
   begin
 if(CLK'event and CLK='1') then 
          if CLR = '1' then 
   IQ(7 downto 0)  <= DR;  --CLR clears and initializes the multiplier
   IQ(15 downto 8) <= (others => '0');
   else 
  if (S='1') then
    IQ <= Cin & IQ(15 downto 1);
  elsif (W='1') then
    IQ(15 downto 8) <= DL;
  end if;
          end if;

 end if;  
    end process;
Q<=IQ;
end shiftregister;

波形

测试平台

library IEEE;
use IEEE.std_logic_1164.all;

entity register_tb is
end register_tb;

architecture register_tb of register_tb is
    component shiftregister is port (
        CLK, CLR: in STD_LOGIC;
        S: in STD_LOGIC; --Shift right
        W: in STD_LOGIC; --Write
        Cin: in STD_LOGIC; --possible carry in from the addition
        DL: in STD_LOGIC_VECTOR (7 downto 0); --left load for addition result
        DR: in STD_LOGIC_VECTOR (7 downto 0); --right load for initial multiplier
        Q: out STD_LOGIC_VECTOR (15 downto 0)
    );
    end component;

    signal CLK: std_logic:='0';
    signal CLR: std_logic:='1';
    signal Cin: std_logic:='0';
    signal S: std_logic:='1';
    signal W: std_logic:='0';
    signal DL, DR: std_logic_vector(7 downto 0):="00000000";
    signal Q: std_logic_vector(15 downto 0):="0000000000000000";
begin 
    U0: shiftregister port map (CLK, CLR, S, W, Cin, DL,DR,Q);

    CLR <= not CLR    after 20 ns;
    CLK <= not CLK    after 5 ns;
    W   <= not W      after 10 ns;
    DL  <= "10101010" after 10 ns;
    DR  <= "00110011" after 10 ns;

end register_tb;

Answer 1

您的模拟显示您的S输入始终很高。设置条件的方式，这意味着最后的elsif语句将不会执行，因为S的优先级高于W。如果您希望您的写作优先于轮班操作，则应该切换条件

if (W='1') then
  IQ(15 downto 8) <= DL;
elsif (S='1') then
  IQ <= Cin & IQ(15 downto 1);
end if;

根据您对所需行为的评论，您可以执行以下操作：

if (S='1' and W='1') then
  IQ  <= Cin & DL & IQ(7 downto 1);
elsif (W='1') then -- S=0
  IQ(15 downto 8) <= DL;
elsif (S='1') then -- W=0
  IQ <= Cin & IQ(15 downto 1);
end if; -- W=0 & S=0

Answer 2

一些改进：

（1）从灵敏度列表中删除除CLK之外的所有信号。您的进程没有异步信号，因此灵敏度列表中只需要时钟。

process(CLK)

（2）仅将零分配给所需的位 - ＆gt;品味问题;）

IQ(7 downto 0)  <= DR;              --CLR clears and initializes the multiplier
IQ(15 downto 8) <= (others => '0');

（3）elsif陈述可以澄清分配优先权：

if (S='1') then
  IQ <= Cin & IQ(15 downto 1);
elsif (W='1') then
  IQ(15 downto 8) <= DL;
end if;

（4）行Q <= IQ;产生第二个16位寄存器。我认为这不是故意的。将此行移到流程之外。