vhdl中的移位寄存器

Question

我正在尝试采用18位并行负载，并使用vhdl中的移位寄存器将其更改为9个2位输出。我已经提出了以下代码，但我不确定我是否正确地考虑了这个问题。

architecture rtl of x is 

signal two_shifter  : std_logic_vector(1 downto 0); 
signal load_data    : std_logic; 
signal shift_enable : std_logic; 

begin 

--Parallel to Serial shifter-- 
shifter: process(clk, reset) 
begin 
  if (reset = '1') then 
     two_shifter <= "00"; 
  elsif rising_edge(clk) then 
    if (load_data = '1') then 
        two_shifter <= data_in; 
    elsif (shift_enable = '1') then 
        two_shifter <= '0' & two_shifter(1); 
    end if; 
  end if; 
end process shifter; 

output_reg: process(clk, reset) 
begin 
if (reset = '1') then 
   data_out <= '0'; 
elsif rising_edge(clk) then 
   data_out <= two_shifter(0); 
end if; 
end process output_reg; 

--Serial to Parallel shifter-- 
input_reg: process(clk, reset) 
begin 
 if (reset = '1') then 
   two_shifter <= "00"; 
 elsif rising_edge(clk) then 
   two_shifter <= two_shifter(1) & receive_data; 
 end if; 
end process input_reg; 

我有2位宽的two_shifter而且我没有把load_data做任何事情。这还行吗？