错误10500针对别名声明

时间:2014-11-05 02:13:27

标签: compiler-errors syntax-error vhdl hdl

我遇到问题的代码将控制字吐成几个部分,以便它们可以被各自的电路使用。

当我尝试编译此代码时,每个别名行会收到两个10500错误: “近文本”别名“;期待”结束“或”(“或标识符或并发语句” “近文”是“;期待”,“或”通用“。

我尝试添加“结束”;别名声明后的“end alias”,但它仍然返回相同的错误。

我还尝试在声明的各个部分添加“signal”,但这仍然会导致相同的错误。

原来我在阻塞之前已经将std_logic_vector转换为bit_vector,而别名输出是位类型而不是std_logic,但我将其更改为std_logic,认为类型转换是问题所在。

--Splits control word into specific sections.
    Architecture split of t11214 is
            Begin
                Alias enable_input: std_logic is instruction(1);
                Alias enable_output: std_logic is instruction(2);
                Alias select_accumulator: std_logic is instruction(3);
                Alias select_operand: std_logic_vector(1 to 2) is instruction(4 to 5);
                Alias select_prcmp: std_logic_vector(1 to 2) is instruction(6 to 7);
                Alias select_prenot: std_logic_vector(1 to 2) is instruction(8 to 9);
                Alias select_function: std_logic_vector(1 to 2) is instruction(10 to 11);
                Alias select_rng: std_logic is instruction(12);
                Alias shift: std_logic_vector(1 to 4) is instruction(13 to 16);
    End architecture split;

1 个答案:

答案 0 :(得分:1)

Alias是声明的一部分,因此它必须<{>> Begin之前,因此如下:

Architecture split of t11214 is
  ...
  Alias enable_input: std_logic is instruction(1);
  ...
Begin
  ...
End architecture split;