Question

我正在处理一个4 x 4位乘法器并收到此错误消息，“错误（10500）：lab_6.vhd（33）处的VHDL语法错误接近文本”after“;期待”）“或”， “”二十次。问题是我在after语句之后有一个“）”或“，”。这是代码：

library ieee;
use ieee.std_logic_1164.all;

entity lab_6 is
 port(x, y :in std_logic_vector(0 to 3);
   f :out std_logic_vector(0 to 7));
end lab_6;

architecture lab_6_arch of lab_6 is
signal sigand0, sigand1, sigand2, sigand3, sigand4, sigand5, sigand6, sigand7, sigand8, sigand9, sigand10, sigand11, sigand12, sigand13, sigand14, sigand15: std_logic;
signal sigha0, sigha1, sigha2, sigha3, sigha4, sigha5, sigha6, sigha7: std_logic;
signal sigfa0, sigfa1, sigfa2, sigfa3, sigfa4, sigfa5, sigfa6, sigfa7, sigfa8, sigfa9, sigfa10, sigfa11, sigfa12, sigfa13, sigfa14, sigfa15: std_logic;
component fa is
 port( x : in std_logic_vector(0 to 2);
    f : out std_logic_vector(0 to 1));
end component;

component a_n_d is
 port( x : in std_logic_vector (0 to 1);
  f : out std_logic);
end component;

component ha is
 port(x :in std_logic_vector(0 to 1);
   f :out std_logic_vector(0 to 1));
end component;

begin

module1: a_n_d
 port map( x(0) => x(0),
   y(0) => x(1),
   f => sigand0 after 3 ns);
f(0)<= sigand0;

module2_1: a_n_d
 port map( x(1) => x(0),
   y(0) => x(1),
   f => sigand1 after 3 ns);
module2_2: a_n_d
 port map( x(0) => x(0),
   y(1) => x(1),
   f => sigand2 after 3 ns);
module2_3:ha
 port map( sigand1 => x(0),
   sigand2 => x(1),
   f(0)=> sigha0 after 4 ns,
   f(1)=> sigha1 after 4 ns);
f(1)<=sigha0;

module3_1: a_n_d
 port map( x(2) => x(0),
   y(0) => x(1),
   f => sigand3 after 3 ns);
module3_2: a_n_d
 port map( x(1) => x(0),
   y(1) => x(1),
   f => sigand4 after 3 ns);
module3_3: a_n_d
  port map( x(0) => x(0),
   y(2) => x(1),
   f => sigand5 after 3 ns);
module3_4:fa
 port map( sigand3 => x(0),
   sigand4=> x(1),
   sigha1=>x(2),
   f(0)=> sigfa0 after 8 ns,
   f(1)=> sigfa1 after 8 ns);
module3_5:ha
 port map( sigfa0 => x(0),
   sigand5=> x(1),
   f(0)=> sigha2 after 4 ns,
   f(1)=> sigha3 after 4 ns);
f(2) <= sigha2;

module4_1: a_n_d
 port map( x(3) => x(0),
   y(0) => x(1),
   f => sigand6 after 3 ns);
module4_2: a_n_d
 port map( x(2) => x(0),
   y(1) => x(1),
   f => sigand7 after 3 ns);
module4_3: a_n_d
 port map( x(1) => x(0),
   y(2) => x(1),
   f => sigand8 after 3 ns);
module4_4: a_n_d
 port map( x(0) => x(0),
   y(3) => x(1),
   f => sigand9 after 3 ns);
module4_5:fa
 port map( sigand6 => x(0),
   sigand7=> x(1),
   sigfa1=>x(2),
   f(0)=> sigfa2 after 8 ns,
   f(1)=> sigfa3 after 8 ns);
module4_6:fa
 port map( sigand8 => x(0),
   sigfa2=> x(1),
   sigha3=>x(2),
   f(0)=> sigfa4 after 8 ns,
   f(1)=> sigfa5 after 8 ns);
module4_7:ha
 port map( sigfa4 => x(0),
   sigand5=> x(1),
   f(0)=> sigha4 after 4 ns,
   f(1)=> sigha5 after 4 ns);
f(3)<=sigha4;

module5_1: a_n_d
 port map( x(3) => x(0),
   y(1) => x(1),
   f => sigand10 after 3 ns);
module5_2: a_n_d
 port map( x(2) => x(0),
   y(2) => x(1),
   f => sigand11 after 3 ns);
module5_3: a_n_d
 port map( x(1) => x(0),
   y(3) => x(1),
    f => sigand12 after 3 ns);

module5_4:ha
 port map( sigfa3 => x(0),
   sigand10=> x(1),
    f(0)=> sigha6 after 4 ns,
    f(1)=> sigha7 after 4 ns);

module5_5:fa
 port map( sigand11 => x(0),
   sigha6=> x(1),
    sigfa5=>x(2),
   f(0)=> sigfa6 after 8 ns,
   f(1)=> sigfa7 after 8 ns);
module5_6:fa
 port map( sigand12 => x(0),
   sigfa6=> x(1),
   sigha5=>x(2),
   f(0)=> sigfa8 after 8 ns,
  f(1)=> sigfa9 after 8 ns);
f(4)<=sigfa8;

module6_1: a_n_d
 port map( x(3) => x(0),
   y(2) => x(1),
   f => sigand13 after 3 ns);
module6_2: a_n_d
 port map( x(2) => x(0),
   y(3) => x(1),
   f => sigand14 after 3 ns);
module6_3:fa
 port map( sigand13 => x(0),
   sigha7=> x(1),
   sigfa7=>x(2),
   f(0)=> sigfa10 after 8 ns,
   f(1)=> sigfa11 after 8 ns);
module6_4:fa
 port map( sigand14 => x(0),
   sigfa9=> x(1),
   sigfa10=>x(2),
   f(0)=> sigfa12 after 8 ns,
    f(1)=> sigfa13 after 8 ns);
 f(5)<=sigfa12;

 module7_1: a_n_d
  port map( x(3) => x(0),
    y(3) => x(1),
    f => sigand15 after 3 ns);
 module7_2:fa
  port map( sigand15 => x(0),
    sigfa11=> x(1),
    sigfa13=>x(2),
   f(0)=> sigfa14 after 8 ns,
   f(1)=> sigfa15 after 8 ns);
 f(6)<=sigfa14;
 f(7)<=sigfa15;
 end lab_6_arch;

感谢您的帮助和时间。

Answer 1

您不能在端口映射中使用任何语句，端口映射仅用于将端口绑定到信号（或封闭层次结构的端口）：

<component_identifier>: <component_name>
port map(
    <port_name> => <assigned_signal>,
    ...
)

您可以做的是将sigand0的分配延迟到f（0）：

module1: a_n_d
    port map( x(0) => x(0),
              y(0) => x(1),
              f => sigand0);

f(0) <= sigand0 after 3 ns;

希望有所帮助！

Answer 2

（注意：我不知道VHDL，我只是按照我在Qualis VHDL Quick Reference Card找到的内容。）

第33行似乎在这里：

module2_1: a_n_d
 port map( x(1) => x(0),
   y(0) => x(1),
   f => sigand1 after 3 ns);     <-- line 33

after子句似乎只能出现在<=而不是=>的语句中。您获得的错误实际上意味着编译器没有期望在那时看到after，而是向您展示它的期望（通常不是非常有用）

错误10500，没有意义

2 个答案: