Question

我对此更新，这是作业，但我试图理解这个真正不一致的错误。我有2个错误;一行在第11行，第一行在第17行，它们都是语法错误

); -- line 11 BEGIN --line 17

整个代码

Library ieee;
Use ieee.std_logic_1164.all;
entity addsub4 is

port(
a: in std_logic_vector(3 downto 0);
b: in std_logic_vector (3 downto 0);
e: in std_logic;
carry: out std_logic;
over: out std_logic;
sout: out std_logic_vector (3 downto 0);
);
end addsub4;

architecture addsub4 of addsub4 is
signal c: std_logic_vector (4 downto 0);
signal bx: std_logic_vector (3 downto 0);
BEGIN
bx <= b xor e&e&e&e;
c(0) <= e;
s <= a xor bx xor c(3 downto 0);
c (4 downto 1) <= (a and bx) or (c(3 downto 0) and (a xor bx));
carry <= c(4);
over <= c(3) xor c(4);
end addsub4;

Answer 1

第一个错误;在PORT声明中，分号是分隔符，而不是终止符。换句话说，最后一个声明;

sout: out std_logic_vector (3 downto 0);

应该只是

sout: out std_logic_vector (3 downto 0)

...因为没有进一步的声明要分开。

VHDL语法错误10500

1 个答案: