错误（10500）：靠近文本“实体”的Project1_Components.vhd（22）处的VHDL语法错误；期待“结束”或声明声明

Question

我正在尝试创建一个AND门包，以便在该项目的另一部分中使用，而且我不知道如何解决此错误。这是我的第一个vhdl项目，我完全不知所措。

我尝试了多种更改语法的方法，包括更改结束行。从所有人的角度看，这似乎是正确的，而且我的书或笔记中没有一个表明声明实体的另一种方式。

library ieee;
use ieee.std_logic_1164.all;

package Project1_Components is

 component AND2
    generic (DELAY: time :=5ns);
    port (in1, in2: in std_logic; out1: out std_logic);
 end component;
 component AND3
    generic (DELAY: time :=5ns);
    port (in1, in2,in3: in std_logic; out1: out std_logic);
 end component; 
 component AND4
    generic (DELAY: time :=5ns);
    port (in1, in2,in3,in4: in std_logic; out1: out std_logic);
 end component;
end package;

package body Project1_Components is

  entity AND2 is
   generic (DELAY: time);
   port (in1, in2: in std_logic; out1: out std_logic);
 end entity;
 entity AND3 is
  generic (DELAY: time);
  port (in1, in2, in3: in std_logic; out1: out std_logic);
 end entity;
  entity AND4 is
   generic (DELAY: time);
   port (in1, in2, in3, in4: in std_logic; out1: out std_logic);
 end entity;

 architecture behavioral of AND2 is
    begin
        out1 <= in1 and in2 after DELAY;
    end architecture;
 architecture behavioral of AND3 is
    begin
        out1 <= in1 and in2 and in3 after DELAY;
    end architecture;
 architecture behavioral of AND4 is
    begin
        out1 <= in1 and in2 and in3 and in4 after DELAY;
    end architecture;
end package;