错误(10500):VHDL语法错误------预期为“(”或标识符(“ others”为保留关键字)或一元运算符

时间:2018-10-24 13:56:27

标签: vhdl

有人可以看到我的代码有什么问题吗?

我从教科书中复制了代码,但是我的书中没有包含一些错误。

这是错误:

library IEEE;
use IEEE.std_logic_1164.all;

entity Moore_State is
port(
    CLK: in STD_LOGIC;
    S: in STD_LOGIC;
    FB: in STD_LOGIC;
    BACK_OUT: out STD_LOGIC;
    FORWARD_OUT: out STD_LOGIC
    );
end Moore_State;

architecture Moore1_arch of Moore_State is
type StateType is (idle,ready,back,forward);
signal state:StateType;
begin
Process(CLK)
begin
if(CLK'event and CLK='1') then

case state is

when idle=>
        if S='1' then state<=ready;
        else state<=idle;
        end if;
when ready=>
        if FB='0' then state<=back;
        else state<=forward;
        end if;
when back=>
        if S='1' then state<=idle;
        else state<=back;
        end if;
when forward=>
        if S='1' then state<=idle;
        else state<=forward;
        end if;

        end case;
    end if;
end Process;

with state select
    BACK_OUT <='1' when back,
            '0' when others;
    FORWARD_OUT <='1' when forward,
            '0' when others;

end Moore1_arch;

,错误消息出现在最后一段:

1.Error(10500):文本“,”附近的VHDL1.vhd(48)处的VHDL语法错误;期待“;”

2.Error(10500):文本“其他”附近的VHDL1.vhd(49)处的VHDL语法错误;期望“(”,或标识符(“ others”是保留关键字)或一元运算符

1 个答案:

答案 0 :(得分:0)

您忘记了第二部分中的with-select语句:

with state select
    BACK_OUT     <= '1' when back,
                    '0' when others;

with state select
    FORWARD_OUT  <= '1' when forward,
                    '0' when others;