generic( -- read cycle
constant taa : time := 120 ns;
constant tacs: time := 120 ns;
constant tclz: time := 10 ns;
constant tchz :time := 10 ns;
constant toh :time := 10 ns;
-- write cycle begins
constant twc : time := 120 ns;
constant taw:time := 105 ns;
constant twp :time := 70 ns;
constant twhz: time := 35 ns;
constant tdw :time := 35 ns;
constant tdh :time := 0 ns;
constant tow :time := 10 ns);
type ramtype is array (0 downto 255) of std_logic_vector(7 downto 0);
signal ram: ramtype :=( others =>(others =>'0'));
if(rising_edge(we) and cs'delayed = '0') or
(falling_edge(cs) and we'delayed = '0') then
ram(conv_integer(address'delayed)) <= to_stdlogicvector(data'delayed); -- error here
data <= transport data'delayed after tow;
end if;
if(falling_edge(we) and cs = '0') then
data <= transport "ZZZZZZZZ" after twhz;
end if;
if (cs'event ='1' and oe = '0') then -- error here
if cs = '1' then
data <= transport "ZZZZZZZZ" after tchz;
elsif we = '1' then
data <= "XXXXXXXX" after tchz;
data <= transport to_stdlogicvector(ram(conv_integer(address))) after tacs; --error here
end if;
end if;
if address'event and cs = '0' and oe = '0' and we = '1' then
data <= "XXXXXXXX" after toh;
data <= transport to_stdlogicvector(ram(conv_integer(address))) after taa; -- error here
end if;
end process;
end Behavioral;
在以下行中出现错误 第77行：期待自然类型。 第77行：索引名称不是std_logic_vector 第72行：找到运算符“=”的'0'定义，无法确定“=”的精确重载匹配定义 第83行：正式没有实际值或默认值。 第83行：期待自然类型。 ine 83：索引名称不是std_logic_vector
无法弄清楚可能出现的确切错误
答案 0 :(得分：0)
好。我填写了它要分析的空白：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity single_port_ram is
generic (
-- read cycle
constant taa: time := 120 ns;
constant tacs: time := 120 ns;
constant tclz: time := 10 ns;
constant tchz: time := 10 ns;
constant toh: time := 10 ns;
-- write cycle begins
constant twc: time := 120 ns;
constant taw: time := 105 ns;
constant twp: time := 70 ns;
constant twhz: time := 35 ns;
constant tdw: time := 35 ns;
constant tdh: time := 0 ns;
constant tow: time := 10 ns
);
port (
address: in std_logic_vector(7 downto 0);
data: inout std_logic_vector(7 downto 0);
we: in std_logic;
cs: in std_logic;
oe: in std_logic
);
end entity;
architecture behavioral of single_port_ram is
type ramtype is array (0 downto 255) of std_logic_vector(7 downto 0);
signal ram: ramtype :=( others =>(others =>'0'));
begin
SINGLE_PROCESS:
process(we, cs, address, data, oe)
begin
if ( rising_edge(we) and cs'delayed = '0') or
(falling_edge(cs) and we'delayed = '0') then
ram(to_integer(unsigned (address'delayed))) <= data'delayed;
-- to_stdlogicvector(data'delayed); -- error here
data <= transport data'delayed after tow;
end if;
if(falling_edge(we) and cs = '0') then
data <= transport "ZZZZZZZZ" after twhz;
end if;
if (cs'event and oe = '0') then -- error here -- cs'event = '1'
if cs = '1' then
data <= transport "ZZZZZZZZ" after tchz;
elsif we = '1' then
data <= "XXXXXXXX" after tchz;
data <= transport std_logic_vector(ram(to_integer(unsigned(address)))) after tacs; --error here
end if;
end if;
if address'event and cs = '0' and oe = '0' and we = '1' then
data <= "XXXXXXXX" after toh;
data <= transport std_logic_vector(ram(to_integer(unsigned(address)))) after taa; -- error here
end if;
end process;
end behavioral;
我没有在没有测试台的情况下担保它的功能。
从无符号类型转换中，您可以在VHDL-2008前程序包numeric_std工具（ghdl）上完成此操作。在2008年，std_logic_vector和unsigned都是std_ulogic_vector的已解析子类型。无符号类型转换是不必要的。
如果我没有弄错的话，你似乎一直在使用IEEE库的Mentor Graphics版本，包std_logic_arith。
注意＆＃39; EVENT返回一个布尔值，并对＆＃39; 1＆＃39;进行相等的测试。没有分析。您仍然存在错误标记注释。
包numeric_std提供to_integer而不是conv_integer。
原版看起来更好，虽然在可能的情况下在BIT类型中实现。
（这最初取自Charles H. Roth，Jr。＆nbsp; 1998年出版的数字系统设计使用VHDL，第9章。当我注意到你的问题的语言避免声称作者身份时，我去看了。）
-- memory model with timing (OE_b=0)
library ieee;
use ieee.std_logic_1164.all;
library bitlib;
use bitlib.bit_pack.all;
entity static_RAM is
generic (
constant tAA: time := 120 ns; -- 6116 static CMOS RAM
constant tACS: time := 120 ns;
constant tCLZ: time := 10 ns;
constant tCHZ: time := 10 ns;
constant tOH: time := 10 ns;
constant tWC: time := 120 ns;
constant tAW: time := 105 ns;
constant tWP: time := 70 ns;
constant tWHZ: time := 35 ns;
constant tDW: time := 35 ns;
constant tDH: time := 0 ns;
constant tOW: time := 10 ns
);
port (
CS_b, WE_b, OE_b: in bit;
Address: in bit_vector(7 downto 0);
Data: inout std_logic_vector(7 downto 0) :=
(others => 'Z')
);
end Static_RAM;
architecture SRAM of Static_RAM is
type RAMtype is array(0 to 255) of bit_vector(7 downto 0);
signal RAM1: RAMtype := (others => (others => '0'));
begin
RAM:
process
begin
if (rising_edge(WE_b) and CS_b'delayed = '0') or
(rising_edge(CS_b) and WE_b'delayed = '0') then
RAM1(vec2int(Address'delayed)) <= to_bitvector(Data'delayed); --write
if CS_b = '0' then
Data <= transport Data'delayed after tOW;
end if;
end if;
if falling_edge(WE_b) and CS_b = '0' then
Data <= transport "ZZZZZZZZ" after tWHZ;
end if;
--read back after write
if CS_b'event and OE_b = '0' then
if CS_b = '1' then
Data <= transport "ZZZZZZZZ" after tCHZ;
elsif WE_b = '1' then --read
Data <= "XXXXXXXX" after tCLZ;
-- RAM is deselected
Data <= transport to_stdlogicvector(RAM1(vec2int(Address))) after tACS;
end if;
end if;
wait on CS_b, WE_b, Address;
end process RAM;
check:
process
begin
if CS_b'delayed = '0' and NOW /= 0 ns then
if address'event then
assert (address'delayed'stable(tWC))
-- tRC = tWC assumed report "Address cycle time too short"
severity WARNING;
end if;
if rising_edge(WE_b) then
assert (address'delayed'stable(tAW))
report "Address not valid long enough to end of write"
severity WARNING;
assert (WE_b'delayed'stable(tWP))
report "Write pulse too short"
severity WARNING;
assert (Data'delayed'stable(tDW))
report "Data setup time too short"
severity WARNING;
wait for tDH;
assert (Data'last_event >= tDH)
report "Data hold time too short"
severity WARNING;
end if;
end if;
wait on WE_b, address, CS_b;
end process check;
end SRAM;
原来转换得很干净：
-- memory model with timing (OE_b=0)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library bitlib;
-- use bitlib.bit_pack.all;
entity static_RAM is
generic (
constant tAA: time := 120 ns; -- 6116 static CMOS RAM
constant tACS: time := 120 ns;
constant tCLZ: time := 10 ns;
constant tCHZ: time := 10 ns;
constant tOH: time := 10 ns;
constant tWC: time := 120 ns;
constant tAW: time := 105 ns;
constant tWP: time := 70 ns;
constant tWHZ: time := 35 ns;
constant tDW: time := 35 ns;
constant tDH: time := 0 ns;
constant tOW: time := 10 ns
);
port (
CS_b, WE_b, OE_b: in std_logic;
Address: in std_logic_vector(7 downto 0);
Data: inout std_logic_vector(7 downto 0) :=
(others => 'Z')
);
end Static_RAM;
architecture SRAM of Static_RAM is
type RAMtype is array(0 to 255) of std_logic_vector(7 downto 0);
signal RAM1: RAMtype := (others => (others => '0'));
begin
RAM:
process
begin
if (rising_edge(WE_b) and CS_b'delayed = '0') or
(rising_edge(CS_b) and WE_b'delayed = '0') then
RAM1(to_integer(unsigned(Address'delayed)))
<= Data'delayed; --write
if CS_b = '0' then
Data <= transport Data'delayed after tOW;
end if;
end if;
if falling_edge(WE_b) and CS_b = '0' then
Data <= transport "ZZZZZZZZ" after tWHZ;
end if;
--read back after write
if CS_b'event and OE_b = '0' then
if CS_b = '1' then
Data <= transport "ZZZZZZZZ" after tCHZ;
elsif WE_b = '1' then --read
Data <= "XXXXXXXX" after tCLZ;
-- RAM is deselected
Data <= transport RAM1(to_integer(unsigned(Address))) after tACS;
end if;
end if;
wait on CS_b, WE_b, Address;
end process RAM;
check:
process
begin
if CS_b'delayed = '0' and NOW /= 0 ns then
if address'event then
assert (address'delayed'stable(tWC))
-- tRC = tWC assumed report "Address cycle time too short"
severity WARNING;
end if;
if rising_edge(WE_b) then
assert (address'delayed'stable(tAW))
report "Address not valid long enough to end of write"
severity WARNING;
assert (WE_b'delayed'stable(tWP))
report "Write pulse too short"
severity WARNING;
assert (Data'delayed'stable(tDW))
report "Data setup time too short"
severity WARNING;
wait for tDH;
assert (Data'last_event >= tDH)
report "Data hold time too short"
severity WARNING;
end if;
end if;
wait on WE_b, address, CS_b;
end process check;
end SRAM;
分析。
<强>附录
提问者评论了BITLIB的使用，所以我去看了。
本书作者有一个资源页面（Digital Systems Design Using VHDL），找到的here中的VHDL源代码由本书中的章节和图号编号索引。 BITLIB库VHDL代码可在Bit_pack.vhd中找到，
昨晚的一点看法也揭示了2008年出版的第二版书。