Question

我设计了一个实体乘法和一个实现这个实体的架构，但我不知道如何编写一个测试平台。换句话说：我如何将值传递给我的架构？我不确定这些代码是否正确，但我无法在不传递值的情况下对其进行测试。

library ieee; 
use ieee.numeric_std.all; 
use ieee.std_logic_1164.all;

entity multiply is
port (
    in_A : in std_ulogic_vector(7 downto 0);
    in_B : in std_ulogic_vector(7 downto 0);
    out_Q : out std_ulogic_vector(15 downto 0)
);
end multiply;

architecture multiply_arch of multiply is
signal p0 : std_ulogic_vector(7 downto 0);
signal p1 : std_ulogic_vector(7 downto 0);
signal p2 : std_ulogic_vector(7 downto 0);
signal p3 : std_ulogic_vector(7 downto 0);
signal p4 : std_ulogic_vector(7 downto 0);
signal p5 : std_ulogic_vector(7 downto 0);
signal p6 : std_ulogic_vector(7 downto 0);
signal p7 : std_ulogic_vector(7 downto 0);
begin
p0 <= (7 downto 0 => in_A(0)) and in_B;
p1 <= (7 downto 0 => in_A(1)) and in_B;
p2 <= (7 downto 0 => in_A(2)) and in_B;
p3 <= (7 downto 0 => in_A(3)) and in_B; 
p4 <= (7 downto 0 => in_A(4)) and in_B;
p5 <= (7 downto 0 => in_A(5)) and in_B;
p6 <= (7 downto 0 => in_A(6)) and in_B; 
p7 <= (7 downto 0 => in_A(7)) and in_B;

out_Q(15 downto 1) <= std_ulogic_vector((unsigned(p0) + unsigned(p1&"0") + unsigned(p2&"00") + unsigned(p3&"000") + unsigned(p4&"0000") + unsigned(p5&"00000") + unsigned(p6&"000000") + unsigned(p7&"0000000")));
end architecture multiply_arch;

Answer 1

您需要创建组件定义，然后在另一个文件中实例化该组件。该文件将是您的测试平台文件。

测试平台文件需要component，如下所示：

component multiply is
port (
    in_A : in std_ulogic_vector(7 downto 0);
    in_B : in std_ulogic_vector(7 downto 0);
    out_Q : out std_ulogic_vector(15 downto 0)
);
end component multiply;

然后在begin的{{1}}语句下方，您需要组件实例化，如下所示：

architecture

您需要从测试平台驱动信号test_A和test_B，并查看信号test_out的结果，看看您的乘法模块是否按预期运行。

有关此内容的完整示例，请参阅：如何create a testbench in VHDL

Answer 2

multiply实体的输入位数很少（只有16 std_logic），没有模块中的时钟或状态，所以一个详尽的测试平台，尝试所有0/1 可以创建输入的组合。该测试台可包括a ＆＃34;参考＆＃34;模型，在乘法运算的情况下，只是*。

下面列出了对此类测试平台的建议：

library ieee;
use ieee.std_logic_1164.all;

entity multiply_tb is
end entity;


library ieee;
use ieee.numeric_std.all;

architecture sim of multiply_tb is

  signal dut_in_a  : std_ulogic_vector( 7 downto 0);
  signal dut_in_b  : std_ulogic_vector( 7 downto 0);
  signal dut_out_q : std_ulogic_vector(15 downto 0);

  signal dut_ok : boolean;

begin

  -- Device Under Test (DUT)
  multiply_e : entity work.multiply
    port map(
        in_A => dut_in_a,
        in_B => dut_in_b,
        out_Q => dut_out_q);

  -- Result generation
  dut_ok <= to_integer(unsigned(dut_in_a)) * to_integer(unsigned(dut_in_b)) =
            to_integer(unsigned(dut_out_q(15 downto 1)));

  -- Stimuli generation and result test
  process is
    variable in_a_v  : natural;
    variable in_b_v  : natural;
    variable out_q_v : natural;
  begin
    for in_a_v in 0 to 255 loop
      for in_b_v in 0 to 255 loop
        dut_in_a <= std_ulogic_vector(to_unsigned(in_a_v, dut_in_a'length));
        dut_in_b <= std_ulogic_vector(to_unsigned(in_b_v, dut_in_b'length));
        wait for 5 ns;
        assert dut_ok report "DUT failed" severity ERROR;
        wait for 5 ns;
      end loop;
    end loop;
    wait;  -- End of simulation
  end process;

end architecture;

请注意，从{0}开始，multiply实体中存在一些错误 out_Q的{{1}}未被驱动，高位不会产生正确的乘法结果。问题解决后，结果生成（参考模型）应酌情更新。

VHDL中的Testbench

2 个答案: