我是vhdl的初学者。我正在尝试编写VHDL代码来描述交通信号灯的行为。它有3个信号输出黄色(0),绿色(1)和红色(2)。最初光是黄色的。 10ns之后它会变成绿色。 40ns后,绿色会变成红色,60ns后红色会变回黄色。状态机没有任何外部输入,是一个由10ns时钟同步的自由运行机器(总时间周期= 10ns)。交通信号灯有一个外部复位控制信号,可将灯重置为黄色。我需要向测试台显示2次复位情况和无符号十进制格式的自由运行输出信号。
vhdl代码在强制时钟和在testbench中删除rst_process的代码时运行正常,但是test-bench的rst_process没有按预期工作(在模拟中未定义)
这是主要的vhdl代码
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity traf is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
Green : out STD_LOGIC;
Red : out STD_LOGIC;
Yellow : out STD_LOGIC);
end traf;
architecture Behavioral of traf is
signal count:integer range 0 to 10 := 0;
signal state:integer range 0 to 2 := 0;
begin
process(clk, rst)
begin
if(rst = '1') then
state <= 0;
Red <= '0';
Green <= '0';
Yellow <= '1';
count <= 0;
elsif clk'event and clk='1' then
case state is
when 0 => --Yellow Light
if(count=1) then
count <= 0;
state <= 1;
else
count <= (count + 1);
Red <= '0';
Green <= '0';
Yellow <= '1';
end if;
when 1 => --Green Light
if(count=4) then
count <= 0;
state <= 2;
else
count <= count + 1;
Red <= '0';
Green <= '1';
Yellow <= '0';
end if;
when 2 => --Red Light
if(count=6) then
count <= 0;
state <= 0;
else
count <= count + 1;
Red <= '1';
Green <= '0';
Yellow <= '0';
end if;
when others =>
state <= 0;
count <= 0;
end case;
end if;
end process;
end Behavioral;
这是测试平台代码
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb is
-- Port ( );
end tb;
architecture Behavioral of tb is
signal clk,rst,Green,Red,Yellow:std_logic;
constant clk_period : time:=10 ns;
component traf is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
Green : out STD_LOGIC;
Red : out STD_LOGIC;
Yellow : out STD_LOGIC
);
end component;
begin
DUT:traf PORT MAP
(
clk=>clk,
rst=>rst,
Green=>Green,
Red=>Red,
Yellow=>Yellow
);
clk_process:process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
rst_process:process
begin
rst <= '0';
wait for clk_period * 15;
rst <= '1';
wait for clk_period;
rst <= '0';
wait for clk_period * 50;
rst <= '1';
wait for clk_period*2;
rst <= '0';
wait;
end proocess;
end Behavioral;