Question

我有以下VHDL文件，我面临问题。最后的总和是始终得到值undefined。

CL_Adder是Carry前瞻加法器，并且作为单独组件检查并且工作正常。 Regstr模块也正常工作。

问题在于reslt，reslt_out1，reslt_out2变量的使用..！

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.CS_Adder_Package.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity movingaverage is
    Port ( sin : in  STD_LOGIC_VECTOR (10 downto 0);
       clk : in  STD_LOGIC;
       rst : in  STD_LOGIC;
          --reslt_in: in std_logic_vector(14 downto 0);
       sout : out  STD_LOGIC_VECTOR (10 downto 0)
          --reslt_out: out std_logic_vector(14 downto 0)
          ); 
end movingaverage;

architecture Structural of movingaverage is

component Regstr is
port ( d : in STD_LOGIC_VECTOR (10 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (10 downto 0));
end component;


component CL_Adder is
Port ( x : in  STD_LOGIC_VECTOR (14 downto 0);
       y : in  STD_LOGIC_VECTOR (14 downto 0);
       cin : in  STD_LOGIC;
       s : out  STD_LOGIC_VECTOR (14 downto 0);
       cout : out  STD_LOGIC);
end component;

signal s: input_array;
signal s_se :std_logic_vector(14 downto 0):=  (others =>'0');
signal s_se1 :std_logic_vector(14 downto 0):=  (others =>'0');
signal s_se2 : std_logic_vector(14 downto 0):=  (others =>'0');
signal reslt : std_logic_vector(14 downto 0):=  (others =>'0');
signal reslt_out1: std_logic_vector(14 downto 0):=  (others =>'0');
signal reslt_out2: std_logic_vector(14 downto 0):=  (others =>'0');
signal c1,c2: std_logic;

begin


u0: for i in 15 downto 1 generate
    u1:regstr port map(s(i-1)(10 downto 0),clk,rst,s(i)(10 downto 0));
end generate u0;

u7:regstr port map(sin,clk,rst,s(0)(10 downto 0));



s_se(14 downto 0) <= sin(10) & sin(10) & sin(10) & sin(10) & sin(10 downto 0);

reslt<= reslt_out2;

u8:CL_Adder port map(s_se,reslt,'0',reslt_out1,c1);

s_se1<= s(15)(10) & s(15)(10) & s(15)(10) & s(15)(10) & s(15)(10 downto 0);
s_se2 <= not(s_se1);

u9:CL_Adder port map(reslt_out1,s_se2,'1',reslt_out2,c2);





Sout <= reslt(14 downto 4); --divide by 16


end Structural;

Answer 1

如果没有更多的代码，我必须添加一些猜测，但看起来有一个 reslt =＆gt;中的设计循环reslt_out1 =＆gt; reslt_out2 =＆gt; reslt，自此代码中的CL_Adder上没有时钟（clk）：

reslt <= reslt_out2;
...
u8:CL_Adder port map(s_se, reslt, '0', reslt_out1, c1);
...
u9:CL_Adder port map(reslt_out1, s_se2, '1', reslt_out2, c2);

这是否是问题的原因取决于你如何看待 “不确定”。在模拟中，循环本身不应导致X（未知），或类似的，但循环提示一个问题。顺便说一句，你提到“变量用法”，但是显示的代码中没有变量;只有信号。

<强>增加：

如果目的是累积该值，则可以使用顺序过程（进行触发器的定时过程）来捕获每次迭代的结果，并在下一次迭代中作为参数出现。然后可以用以下过程替换reslt <= reslt_out2;：

process (clk, rst) is
begin
  if rst = '1' then  -- Reset if required
    reslt <= (others => '0');
  elsif rising_edge(clk) then  -- Clock
    reslt <= reslt_out2;
  end if;
end process;

VHDL：值不传播到端口映射

1 个答案: