Question

在我的设计中，其中一个VHDL模块有一个使能输入，当计数器达到0时激活该输入。我注意到只有当我从整体设计中驱动使能信号时才激活该特定的VHDL模块... < / p>

也就是说，当馈送使能线的信号连接到整个设计的输出端口时。有人能帮助我吗？代码在

之下

entity SSCtrl is
port(
clk: in STD_LOGIC;
rst: in STD_LOGIC;
ssCEout : out STD_LOGIC;
SSEG_CA : out  STD_LOGIC_VECTOR (7 downto 0);
SSEG_AN : out  STD_LOGIC_VECTOR (3 downto 0);
ssCEout: out STD_LOGIC
);
end SSCtrl;

architecture Behavioral of SSCtrl is

signal clk10Mhz: STD_LOGIC;
signal cnt: NATURAL range 9999 downto 0 := 9999;
signal ssCE: STD_LOGIC := '0';


component dcm
port(
  CLK_IN1           : in     STD_LOGIC;
  CLK_OUT1          : out    STD_LOGIC;
  RESET             : in     STD_LOGIC;
  LOCKED            : out    STD_LOGIC
 );
end component;
component SSCtrlFSM
port(
clk: in STD_LOGIC;
CE: in STD_LOGIC;
ca0: in  STD_LOGIC_VECTOR(7 downto 0);
ca1: in STD_LOGIC_VECTOR(7 downto 0);
ca2: in STD_LOGIC_VECTOR(7 downto 0);
ca3: in STD_LOGIC_VECTOR(7 downto 0);
SSEG_CA : out  STD_LOGIC_VECTOR (7 downto 0);
SSEG_AN : out  STD_LOGIC_VECTOR (3 downto 0)
);
end component;

begin

ssCEout <= ssCE -- ONLY WORKS WITH THIS 

dcm10Mhz : dcm
port map(
CLK_IN1 => clk,
   CLK_OUT1 => clk10Mhz,
RESET => rst
);
ss:SSCtrlFSM
port map(
clk => clk10Mhz,
CE => ssCE,
ca0 => "11000000",
ca1 => "11111001",
ca2 => "10100100",
ca3 => "10110000",
SSEG_CA => SSEG_CA,
SSEG_AN => SSEG_AN
);
process(clk10Mhz)
begin
if(rising_edge(clk10Mhz)) then
if(cnt = 0) then
    cnt <= 9999;
    ssCE <= '1';
else
    cnt <= cnt -1;
    ssCE <= '0';
end if;
end if;
end process;
end Behavioral;

这是内部模块的HDL

entity SSCtrlFSM is
port(
    clk: in STD_LOGIC;
    CE: in STD_LOGIC;
    ca0: in  STD_LOGIC_VECTOR(7 DOWNTO 0);
    ca1: in STD_LOGIC_VECTOR(7 DOWNTO 0);
    ca2: in STD_LOGIC_VECTOR(7 DOWNTO 0);
    ca3: in STD_LOGIC_VECTOR(7 DOWNTO 0);
    SSEG_CA : out  STD_LOGIC_VECTOR (7 downto 0);
    SSEG_AN : out  STD_LOGIC_VECTOR (3 downto 0)
);
end SSCtrlFSM;

architecture Behavioral of SSCtrlFSM is

signal ca: STD_LOGIC_VECTOR(7 downto 0);
signal an: STD_LOGIC_VECTOR(3 downto 0);
type state_type is (st0, st1, st2, st3);
signal state, nstate: state_type := st0;

begin

SSEG_CA <= ca;
SSEG_AN <= an;

process(clk)
begin
if(rising_edge(clk)) then
if(CE = '1') then
    state <= nstate;
end if;
end if;
end process;

nstate_logic: process(state)
begin
nstate <= state;
case(state) is
when st0 =>
    nstate <= st1;
when st1 =>
    nstate <= st2;
when st2 =>
    nstate <= st3;
when st3 =>
    nstate <= st0;
end case;
end process;

output_logic: process(state, ca0, ca1, ca2, ca3)
begin
ca <= "10110000";
an <= "1111";
case(state) is
when st0 =>
    ca <= ca0;
    an <= "0111";
when st1 =>
    ca <= ca1;
    an <="1011";
when st2 =>
    ca <= ca2;
    an <="1101";
when st3 =>
    ca <= ca3;
    an <="1110";
end case;
end process;

end Behavioral;

具有单周期使能的VHDL模块

0 个答案: