Question

attribute ram_style: string;
attribute ram_style of ram : signal is "distributed";

type dist_ram is array (0 to 99) of std_logic_vector(7 downto 0);
signal ram : dist_ram := (others => (others => '0'));

begin

--Pseudocode 
PROCESS(Clk)
BEGIN
    if(rising_edge(Clk)) then
            ram(0) <= "0";
            ram(2) <= "1";
            ram(3) <= "2";
            ram(4) <= "3";
            ram(5) <= "1";
            ram(6) <= "2";
    ...
    ...
        ram(99) <= "3";
    end if; 
END PROCESS;

在上面的场景中，完整的ram在1个时钟周期内更新，但是如果我使用Block ram代替，我需要至少100个时钟周期来更新整个内存，而不是1个时钟周期用作a分发ram。

我也明白，不建议将分布式ram用于大型因为它会耗尽FPGA资源。那么为了达到最佳吞吐量，这种情况的最佳设计是什么（比如几KB KB）。

假设Xilinx FPGA，我应该使用块ram还是分布式ram。非常感谢您的建议。

Thanks for your replies, let me make it a bit more clear.

My purpose is not for ram initialization, 
i have 100 x 20 (8 bits) ram block which needs to be updated after 
certain computation.

After these computations i have to store and then use it back for next iteration.

This is an iterative process and i am expected to finish atleast 2 iterations
within 3000 clk cycles.

if i use the block ram to store these coefficients then to just read and write 
i would need atleast (100*20) cycles with some latency which will not meet my 
requirement.

So how should i go about designing in this case.

Answer 1

你想达到什么目的？您真的需要在1个时钟周期内更新整个RAM，还是可以将其分解为多个时钟周期？

如果你可以把它分解成许多时钟你可以做类似的事情：

PROCESS(Clk)
BEGIN
  if(rising_edge(Clk)) then
    ram(index) <= index;
    index <= index + 1;
  end if; 
END PROCESS;

您也可以初始化块ram。具体细节取决于您的FPGA供应商。因此，对于Xilinx FPGA，请看本文：

http://www.xilinx.com/itp/xilinx10/isehelp/pce_p_initialize_blockram.htm

如果你真的无法将它分解成多个时钟并且你想要多次“初始化”它，那么你将需要像上面那样使用分布式ram。

FPGA Ram设计问题

1 个答案: