Question

我有以下verilog代码。想法是在重置时存储计数器的值。但是，我不确定它是否可以合成（存储器需要同步复位）。我得到了DRC违规，内存，bufreadaddr，bufreadval都被优化了。还有什么其他方式来写这个？

module counter (clk,reset, d_out,laststoredvalue, bufreadaddr, bufreadval, resetcount) ;
input clk ,reset ;
input [5:0] resetcount;

output [15:0] d_out;
output [15:0] laststoredvalue;
input [5:0] bufreadaddr;
output [15:0] bufreadval;
reg [15:0] bufreadval;

reg [15:0] laststoredvalue;

reg [15:0] d_out;
reg [15:0] d_out_mem[63:0];

always @(negedge reset or posedge clk) begin
        if (reset == 0) begin
             d_out <= 16'h0000;
             d_out_mem[resetcount] <= d_out;
             laststoredvalue <= d_out;
         end else begin
              d_out <= d_out + 1'b1; 
          end
end

always @(bufreadaddr)
        bufreadval = d_out_mem[bufreadaddr];


integer count;
initial begin
  count = 0;
end
always @(posedge clk ) begin
    count = count + 1;
    //$display(count);
end


endmodule

Answer 1

嗨，我对你的代码进行了一些小改动;添加了一个临时变量来将输出存储在寄存器中，它将在复位时存储先前的值;

module counter (clk,reset, d_out,laststoredvalue, bufreadaddr, bufreadval, resetcount) ;
input clk ,reset ;
input [5:0] resetcount;

output [15:0] d_out;
output [15:0] laststoredvalue;
input [5:0] bufreadaddr;
output [15:0] bufreadval;
reg [15:0] bufreadval;

reg [15:0] laststoredvalue;
reg [15:0] temp;
reg [15:0] d_out;
reg [15:0] d_out_mem[63:0];

always @(negedge reset or posedge clk) begin
        if (reset == 0) begin

             d_out_mem[resetcount] = d_out;
             laststoredvalue = temp;
                 d_out  = #10 16'h0000;
         end 
            else begin

              d_out = d_out + 1'b1;
                    temp = d_out; 
          end
end

always @(bufreadaddr)
        bufreadval = d_out_mem[bufreadaddr];

endmodule

其余代码与原样相同。

Verilog：置位复位时存储计数器值

1 个答案: