Question

我对这个计数器有疑问。输出都是xxxxxxxx，我知道我应该将count的初始值和溢出设置为0但是它会产生错误。这是代码：

// Code your design here
module counter (in, start, count, clk, overflow);

input [3:0] in;
input clk;
input start;
output reg [7:0] count;
output reg overflow;
//reg count;
//count =0;
//overflow=0;
always @ (posedge clk)
  begin
    if (start) begin
      count <= 8'b0;
      overflow <= 1'b0;
    end

    else if (in == 4'b0101) begin
      count <= count+1;
    end
    if (count == 4'b1111) begin
      overflow <=1'b1;
    end
  end

endmodule

这是测试平台：

// Code your testbench here
// or browse Examples
module tb();

  reg [3:0] in;
  reg clk,start;
  wire [7:0] count;
  reg overflow = 1'b0;

  initial begin

    $display ("time\t clk start in count overflow");
    $monitor ("%g\t %b %b %b %b", $time, clk, start, in, count, overflow);

    clk=0;
    in=0;
    start=0;
   // overflow=0;
   // count=0;

    #5 in=4'd1;
    #5 in=4'd5;
    #5 in=4'd4;
    #5 in=5'd5;
    #5 in=4'd1;
    #5 in=4'd5;
    #5 in=4'd4;
    #5 in=5'd5;
    #5 in=4'd1;
    #5 in=4'd5;
    #5 in=4'd4;
    #5 in=5'd5;
    #5 in=4'd1;
    #5 in=4'd5;
    #5 in=4'd4;
    #5 in=5'd5;
    #50 $finish;

  end

    always #5 clk=~clk;

  counter u0(.*);

endmodule

我知道这是一个简单的问题，但如果你们帮帮忙，我感激不尽。

Answer 1

有两个问题需要解决。

1）仅在时钟的下降沿设置= 5。这是因为clk循环是＃10并且tb代码每＃5改变“in”值。当计数器检查posedge中的in值时它错过了in = 5。在设置信号“in”之前，时间段需要为＃10或TB可以等待clk的结果。

2）需要为计数器设置启动以重置，否则count = x（未知）和count + 1 =＆gt;的值。 x + 1等于x。因此，计数器不会增加并继续保持x。

更新后的tb如下。

module tb();

  reg [3:0] in;
  reg clk,start;
  wire [7:0] count;
  reg overflow = 1'b0;

  initial begin

    $display ("time\t clk start in count overflow");
    $monitor ("%g\t %b %b %b %b", $time, clk, start, in, count, overflow);

    clk=0;
    in=0;
    start=0;
   // overflow=0;
   // count=0;

    #10 start = 1'b1; // reset counter 
    #10 start = 1'b0;
    #10 in=4'd1;
    #10 in=4'd5;
    #10 in=4'd4;
    #10 in=5'd5;
    #10 in=4'd1;
    #10 in=4'd5;
    #10 in=4'd4;
    #10 in=5'd5;
    #10 in=4'd1;
    #10 in=4'd5;
    #10 in=4'd4;
    #10 in=5'd5;
    #10 in=4'd1;
    #10 in=4'd5;
    #10 in=4'd4;
    #10 in=5'd5;
    #50 $finish;

  end

    always #5 clk=~clk;

  counter u0(.*);

initial  // Dump waveform for debug 
$dumpvars;

endmodule

您可以使用$ dumpvars命令转储波形进行调试。

替代代码（使用posedge事件来驱动测试平台中的数据）

// Code your testbench here
// or browse Examples
module tb();

  reg [3:0] in;
  reg clk,start;
  wire [7:0] count;
  reg overflow = 1'b0;

  initial begin

    $display ("time\t clk start in count overflow");
    $monitor ("%g\t %b %b %b %b", $time, clk, start, in, count, overflow);

    clk=0;
    in=0;
    start=0;
   // overflow=0;
   // count=0;

    @(posedge clk )   start = 1'b1;// reset counter 
    @(posedge clk )   start = 1'b0;
    @(posedge clk )   in=4'd1;
    @(posedge clk )   in=4'd5;
    @(posedge clk )   in=4'd4;
    @(posedge clk )   in=5'd5;
    @(posedge clk )   in=4'd1;
    @(posedge clk )   in=4'd5;
    @(posedge clk )   in=4'd4;
    @(posedge clk )   in=5'd5;
    @(posedge clk )   in=4'd1;
    @(posedge clk )   in=4'd5;
    @(posedge clk )   in=4'd4;
    @(posedge clk )   in=5'd5;
    @(posedge clk )   in=4'd1;
    @(posedge clk )   in=4'd5;
    @(posedge clk )   in=4'd4;
    @(posedge clk )   in=5'd5;
    #50 $finish;

  end

    always #5 clk=~clk;

  counter u0(.*);

initial
$dumpvars;

endmodule

计数器系统verilog代码

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