Up Down计数器代码

时间:2014-12-05 22:26:03

标签: verilog

我的项目需要帮助,这是一个从0到20计数或减少的计数器。我已经完成了我的计数器代码,它正在使用主动HDL。但现在我需要在nexys 3 FPGA板中显示7段中的数字。

我有段的代码,但是当我调用段模块时遇到问题 - 它在主动HDL中给出了一个错误。你能告诉我这是什么错误吗?

这是我目前的代码:

module main
    #(parameter N=7)
    (
    input switch,
    input button,
    input fastclk,
    output [3:0] enable,
    output reg[6:0] out
    );    
    wire[N:0]count;
    wire slowclk;

    clock c1(fastclk,slowclk);
    Updown u1(switch,button,slowclk,count);
    segment s1([3:0]count,[7:4]count,fastclk,enable,out); 
    endmodule


module clock(fastclk,slowclk); //clock code
    input fastclk;
    output wire slowclk;
    reg[25:0]period_count = 0;

    always @(posedge fastclk)
        begin
            period_count <= period_count + 1;
        end
    assign slowclk = period_count[25];
endmodule

module Updown // UpDown Counter
#(parameter N=7)    
    (
    input switch,
    input button,
    input clk,
    output reg [N:0]count=8'd0,
    );  


always @(posedge clk)
    begin

        if(switch == 1 && button == 1)  // Countup from 0 to 20
            begin 
                if(count == 8'd20)
                    count <= 0 ;

                else 
                    count <= count +1;

            end
        else if(switch == 0 && button == 1) // Countdown from 20 to 0
        begin 
                if(count == 8'd0)
                    count <= 8'd20 ;

                else 
                    count <= count -1;

            end 
        else count <=8'd0;  
    end
endmodule

module mux(A,B,sel,Y); // 2x1 Multiplexer
    input [3:0]A;
    input [3:0]B;
    input sel;
    output [3:0]Y;
    reg [3:0]Y;

    always @(*)
        begin 
            if(sel==0)
                Y=A;
            else 
                Y=B;

            end
endmodule

module hex7seg(input wire [3:0]x , output reg[6:0]a_to_g); // Hex to 7seg Code

    always @(*)

        case(x)
            0: a_to_g = 7'b0000001; 
            1: a_to_g = 7'b1001111;
            2: a_to_g = 7'b0010010;
            3: a_to_g = 7'b0000110;
            4: a_to_g = 7'b1001100;
            5: a_to_g = 7'b0100100;
            6: a_to_g = 7'b0100000;
            7: a_to_g = 7'b0001111;
            8: a_to_g = 7'b0000000;
            9: a_to_g = 7'b0000100;
            'hA: a_to_g = 7'b0001000;
            'hB: a_to_g = 7'b1100000;
            'hC: a_to_g = 7'b0110001;
            'hD: a_to_g = 7'b1000010;
            'hE: a_to_g = 7'b0110000;
            'hF: a_to_g = 7'b0111000;
            default: a_to_g = 7'b0000001;
        endcase
endmodule

module segment (a,b,fast,enable,seg7);
    input [3:0]a;
    input [3:0]b;
    input fast;
    output [3:0] enable;
    output [6:0] seg7;
    wire [3:0]e1 = 4'b1110;
    wire [3:0]e2 = 4'b1101;
    wire slow;
    wire [3:0]number;

    clock c1(fast,slow);
    mux m1(a,b,slow,number);
    mux m2(e1,e2,slow,enable);
    hex7seg h1(number,seg7);

endmodule

2 个答案:

答案 0 :(得分:1)

segment模块初始化部分代码中有一个小错误:

segment s1([3:0]count,[7:4]count,fastclk,enable,out); 

这部分代码应该看起来有点不同:

segment s1(count[3:0],count[7:4],fastclk,enable,out); 

答案 1 :(得分:1)

  1. 最大的问题是:

    segment s1([3:0]count,[7:4]count,fastclk,enable,out);
    

    应该是:

    segment s1(count[3:0],count[7:4],fastclk,enable,out);
    

    其他选项(IEEE Std 1364-2001按名称自动连接(.*))

    segment s1(.a(count[3:0]), .b(count[7:4]), .fast(fastclk), .seg7(out), .*);
    
  2. 某些模拟器可能会在端口列表中使用ANSI样式端口列表或尾随逗号的输出上抱怨初始值。所以这个:

    output reg [N:0]count=8'd0,
    );
    

    应该是:

    output reg [N:0] count
    );
    initial count=8'd0;
    

    我更喜欢能够控制设计中的重置,所以我更喜欢:

    input reset_n,
    output reg [N:0] count
    );
    always @(posedge clk
      // or negedge reset_n // <-- uncomment for asynchronous reset
      ) begin
      if (!reset_n) begin
        count=8'd0;
      end
      else begin
        // synchronous code here
      end
    end
    
  3. main output reg[6:0] out您有main。由于out不是由wire中的always-block分配的(子模块不计算),因此它应该是reg而不是{{1}}。这是一个指南,因为它是Verilog的最佳实践,大多数模拟都可以容忍它。