Question

我正在尝试制作一个4位上/下modulo10计数器。 Button1 - 计数，Button2 - 倒计时。我正在尝试使用rising_edge命令，但对于两个信号，我无法用按钮定义按下。因此，在下一版本的程序中，我想使用if语句检测按钮。

library IEEE;
use IEEE.std_logic_1164.all, IEEE.numeric_std.all;

ENTITY counter is
generic (n:natural :=4);
port(
button1:        in std_logic;
button2:        in std_logic;
clear:  in std_logic;
C                               : out std_logic;
OUT1                            : out std_logic_vector(n-1 downto 0)
);
END counter;

ARCHITECTURE beh of counter is
begin

p0:process (button1, clear) is
variable count: unsigned (n-1 downto 0);
begin
        if clear = '1' then
        count:= (others=>'0');
                elsif button1='1' then
                count:=count+1;
                        elsif count=10 then
                                count:=(others=>'0');
                                C<='1';
                                else C<='0';
                        end if;

            if button2='1' then
                  count:=count-1;
                  if count=0 then
                        count:=(others=>'1');
                        C<='1';
                        else C<='0';
                  end if;
                  end if;
        OUT1<=std_logic_vector(count);
end process p0;
end architecture beh;

在Quartus程序编译时没有错误，但在模拟中不起作用。我会非常感谢你的帮助。：）

Answer 1

你应该使用CLOCK信号来使用rising_edge，我在你的实体中创建了一个时钟信号：

clock : in std_ulogic;

在此之后你应该对你的过程敏感地发出CLOCK信号和button2信号，如下所示：

p0:process (button1, button2, clear, clock) is

我对此条件的模拟工作正常，当我按下按钮1时，计数会上升，当我按下按钮2时，计数会下降。

完整的架构：

ARCHITECTURE beh of counter is
begin

p0:process (button1, button2, clear, clock) is
variable count: unsigned (n-1 downto 0);
begin
        if rising_edge(clock) then
            if clear = '1' then
                count:= (others=>'0');
            end if;
            if (button1='1') then
                count:=count+1;
            elsif (count=10) then
                count:=(others=>'0');
                C<='1';
            else 
                C<='0';
            end if;

            if (button2='1') then
                  count:=count-1;
            if count=0 then
                  count:=(others=>'1');
                  C<='1';
            else 
            C<='0';
            end if;
            end if;
         end if;
        OUT1<=std_logic_vector(count);
end process p0;
end architecture beh;

VHDL：带有两个按钮的向上/向下计数器

1 个答案: