4位加/减计数器中的危险

时间:2018-02-08 20:27:07

标签: vhdl counter

我们正在尝试使用4位向上和向下计数器来停止计数,或者加载一个数字然后开始计数。

当我们进行路径后模拟时会出现问题。当时钟为'0'时,输出会发生变化,每次输出变化时,有多个危险/毛刺持续约25-30 ps。
(点击放大)

有人可以解释为什么会这样吗?

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

entity esame2 is
    Port ( clock : in  STD_LOGIC;
       reset : in  STD_LOGIC;
       start_stop : in  STD_LOGIC;
       up_down : in  STD_LOGIC;
       value : in  STD_LOGIC_VECTOR (3 downto 0);
       insert : in  STD_LOGIC;
       num : out  STD_LOGIC_VECTOR (3 downto 0));
end esame2;

architecture RTL of esame2 is
    signal vet : STD_LOGIC_VECTOR (3 downto 0);
begin
    process(reset, clock)
    begin 
        if reset = '1' then
            vet <= "0000";
        elsif (clock'event and clock = '1') then
            if(start_stop = '0' and reset = '0') then
                vet <= vet;
            elsif(insert = '1' and start_stop = '1' and reset = '0') then
                vet <= value;            
            elsif(insert = '0' and reset = '0' and start_stop='1' and up_down ='1')then
                if(vet = "1111") then
                    vet <= "0000";
                    else vet <= vet + 1;
                end if;
            elsif(up_down = '0')then
                if(vet = "0000") then
                    vet <= "1111";
                    else vet <= vet - 1;
                end if;
            end if;
        end if;
    end process;
    num <= vet;
end RTL;

0 个答案:

没有答案