Question

我在VHDL中创建了一个双端口寄存器库，我想测试它以确保它有效。我该怎么做呢？我知道我想做什么（将寄存器2设置为常量，在测试程序中读出它，写入寄存器3并将其读回，看看我是否有相同的结果）。

唯一的问题是，我是VHDL的新手，所以我不知道是否有控制台或测试程序是如何构建的，或者如何实例化寄存器文件，甚至是编译它的内容（我是到目前为止一直在使用quartus。）

这是我的注册文件：

use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

-- Register File

entity RF is

port(
    signal clk, we: in std_logic;
    signal ImmediateValue : in std_logic_vector(15 downto 0);
    signal RegisterSelectA, RegisterSelectB : in integer range 0 to 15;

    signal AOut, BOut : out std_logic_vector(15 downto 0)
);

end RF

architecture behavior of RF is

    array std_logic_vector_field is array(15 downto 0) of std_logic_vector(15 downto 0);
    variable registers : std_logic_vector(15 downto 0);

    process (clk, we, RegisterSelectA, RegisterSelectB, ImmediateValue)
        wait until clk'event and clk = '1';
        registers(RegisterSelectA) := ImmediateValue when we = '1';
        AOut <= registers(RegisterSelectA);
        BOut <= registers(RegisterSelectB);
    end process;

end behavior;

Answer 1

首先，如果您不熟悉VHDL设计，最好从网上教程开始，或者抓一本像"The Designer's Guide to VHDL"这样的书。

无论如何，就像软件设计一样，要测试VHDL设计，你必须编写一些测试代码。在硬件设计中，通常这些测试都是单元测试，但通常称为"testbenches"。

对于你给出的设计，你需要创建这样的东西：

library ieee.std_logic_1164.all;
library ieee.numeric_std.all;

entity test_RF is
end entity;

architecture test of test_RF is
  signal clk, we: std_logic;
  signal ImmediateValue : std_logic_vector(15 downto 0);
  signal RegisterSelectA, RegisterSelectB : integer range 0 to 15;
  signal AOut, BOut : std_logic_vector(15 downto 0)
begin

  -- Instantiate the design under test
  u_RF : entity work.RF
  port map (
    clk => clk,
    we  => we,
    ImmediateValue => ImmediateValue,
    RegisterSelectA => RegisterSelectA,
    RegisterSelectB => RegisterSelectB,
    AOut => AOut,
    BOut => BOut
  );

  -- create a clock
  process is
  begin
    clk <= '0';
    loop
      wait for 10 ns;
      clk <= not clk;
    end loop;
  end process;

  -- create one or more processes to drive the inputs and read the outputs
  process is
  begin
    wait until rising_edge(clk);
    -- do stuff
    -- use assert to check things
    -- etc
  end process;

end architecture;

如何测试VHDL文件

1 个答案: